SNVSBJ2A April   2022  – September 2023 TPS38

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1.     8
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR1 / MR) and (CTR2 / MR) Input
      7. 8.3.7 Adjustable Voltage Thresholds
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Voltage – Fast AC Signal Monitoring For Power Fault Detection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Dissipation and Device Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

Table 8-4 Undervoltage Detect Functional Mode Truth Table
DESCRIPTION SENSE CTR (1) / MR PIN VDD PIN OUTPUT (2)
(RESET PIN)
PREVIOUS CONDITION CURRENT CONDITION
Normal Operation SENSE > VITN(UV) SENSE > VITN(UV) Open or capacitor connected VDD > VDD(MIN) High
Undervoltage Detection SENSE > VITN(UV) SENSE < VITN(UV) Open or capacitor connected VDD > VDD(MIN) Low
Undervoltage Detection SENSE < VITN(UV) SENSE > VITN(UV) Open or capacitor connected VDD > VDD(MIN) Low
Normal Operation SENSE < VITN(UV) SENSE > VITN(UV) + HYS Open or capacitor connected VDD > VDD(MIN) High
Manual Reset SENSE > VITN(UV) SENSE > VITN(UV) Low VDD > VDD(MIN) Low
UVLO Engaged SENSE > VITN(UV) SENSE > VITN(UV) Open or capacitor connected VPOR < VDD < VDD(MIN) Low
Below VPOR, Undefined Output SENSE > VITN(UV) SENSE > VITN(UV) Open or capacitor connected VDD < VPOR Undefined
(1) Reset time delay is ignored in the truth table
(2) Open-drain active low output. External pull-up resistor to high voltage
Table 8-5 Overvoltage Detect Functional Mode Truth Table
DESCRIPTION SENSE CTR (1) / MR PIN VDD PIN OUTPUT (2)
(RESET PIN)
PREVIOUS CONDITION CURRENT CONDITION
Normal Operation SENSE < VITN(OV) SENSE < VITN(OV) Open or capacitor connected VDD > VDD(MIN) High
Overvoltage Detection SENSE < VITN(OV) SENSE > VITN(OV) Open or capacitor connected VDD > VDD(MIN) Low
Overvoltage Detection SENSE > VITN(OV) SENSE < VITN(OV) Open or capacitor connected VDD > VDD(MIN) Low
Normal Operation SENSE > VITN(OV) SENSE < VITN(OV) - HYS Open or capacitor connected VDD > VDD(MIN) High
Manual Reset SENSE < VITN(OV) SENSE < VITN(OV) Low VDD > VDD(MIN) Low
UVLO Engaged SENSE < VITN(OV) SENSE < VITN(OV) Open or capacitor connected VPOR < VDD < UVLO Low
Below VPOR, Undefined Output SENSE < VITN(OV) SENSE < VITN(OV) Open or capacitor connected VDD < VPOR Undefined
(1) Reset time delay is ignored in the truth table
(2) Open-drain active low output. External pull-up resistor to high voltage