The TPS3808Gxx-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and MR return above their thresholds.
The TPS3808Gxx-Q1 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808Gxx-Q1 has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications. The device is available in a small SOT-23 package (one option available in WSON) and is fully specified over a temperature range of –40°C to +125°C (TJ).
For more information about TI's voltage supervisor portfolio, visit the Supervisor and Reset IC Overview Page page.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS3808Gxx-Q1 | SOT-23 (6) | 2.90 mm × 1.60 mm |
WSON (6) | 2.00 mm × 2.00 mm |
Changes from I Revision (June 2015) to J Revision
Changes from H Revision (June 2012) to I Revision
Changes from G Revision (November, 2010) to H Revision
ORDERABLE PART NUMBER | NOMINAL SUPPLY VOLTAGE | THRESHOLD VOLTAGE (VIT) |
---|---|---|
TPS3808G01QDRVRQ1 | Adjustable | 0.405 V |
TPS3808G01QDBVRQ1 | ||
TPS3808G12QDBVRQ1 | 1.2 V | 1.12 V |
TPS3808G125QDBVRQ1 | 1.25 V | 1.16 V |
TPS3808G15QDBVRQ1 | 1.5 V | 1.4 V |
TPS3808G18QDBVRQ1 | 1.8 V | 1.67 V |
TPS3808G30QDBVRQ1 | 3 V | 2.79 V |
TPS3808G33QDBVRQ1 | 3.3 V | 3.07 V |
TPS3808G50QDBVRQ1 | 5 V | 4.65 V |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOT-23 | WSON | ||
CT | 4 | 3 | I | Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives user-programmable delay time. See the Selecting the Reset Delay Time for more information. |
GND | 2 | 5 | — | Ground |
MR | 3 | 4 | I | Manual reset. Driving this pin low asserts RESET. MR is internally tied to VDD by a 90-kΩ pullup resistor. |
RESET | 1 | 6 | O | Reset. This is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup resistor from 10 kΩ to 1 MΩ must be used on this pin and allows the reset pin to attain voltages higher than VDD. |
SENSE | 5 | 2 | I | Voltage sense. This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage (VIT), RESET is asserted. |
VDD | 6 | 1 | I | Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin. |
Thermal Pad | — | Pad | — | Thermal pad; connect to ground plan to enhance thermal performance of the package. |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VDD | Input voltage | –0.3 | 7 | V | ||
VCT | CT voltage | –0.3 | (VDD + 0.3) | V | ||
VMR, VRESET, VSENSE |
MR, RESET, SENSE voltage | –0.3 | 7 | V | ||
IRESET | RESET pin current | 5 | mA | |||
TJ | Operating junction temperature(2) | –40 | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||||
---|---|---|---|---|---|---|---|
TPS3808G125QDBVRQ1 IN SOT-23 PACKAGE | |||||||
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |||
Charged device model (CDM), per AEC Q100-011 | ±1000 | ||||||
Machine Model (MM) | ±50 | ||||||
TPS3808GXX-Q1 IN SOT-23 PACKAGE | |||||||
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |||
Charged device model (CDM), per AEC Q100-011 | ±500 | ||||||
TPS3808G01QDRVRQ1 IN SON PACKAGE | |||||||
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |||
Charged device model (CDM), per AEC Q100-011 | ±500 | ||||||
Machine Model (MM) | ±50 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD input supply | 1.8 | 6.5 | V | ||
VSENSE SENSE pin voltage | 0 | VDD | V | ||
MR Manual reset pin voltage | 0 | VDD | V |
THERMAL METRIC(1) | TPS3808Gxx-Q1 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23) | DRV (WSON) | |||
6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 180.9 | 178.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 117.8 | 95.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 27.8 | 135 | °C/W |
ψJT | Junction-to-top characterization parameter | 18.9 | 6.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 27.3 | 136.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | 7.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VDD | Input supply range | 1.8 | 6.5 | V | |||
IDD | Supply current (into VDD pin) | VDD = 3.3 V, RESET not asserted, MR, RESET, CT open | 2.4 | 5 | μA | ||
VDD = 6.5 V, RESET not asserted, MR, RESET, CT open | 2.7 | 6 | |||||
VOL | Low-level output voltage | 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA | 0.3 | V | |||
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA | 0.4 | ||||||
Power-up reset voltage(1) | VOL (max) = 0.2 V, I RESET = 15 μA | 0.8 | V | ||||
VIT | Negative-going input threshold accuracy | TPS3808G01-Q1 | –2% | ±1% | 2% | ||
VIT ≤ 3.3 V | –1.5% | ±0.5% | 1.5% | ||||
3.3 V < VIT ≤ 5 V | –2% | ±1% | 2% | ||||
VIT ≤ 3.3 V | –40°C < TJ < 85°C | –1.25% | ±0.5% | 1.25% | |||
3.3 V < VIT ≤ 5 V | –1.5% | ±0.5% | 1.5% | ||||
VHYS | Hysteresis on VIT pin | TPS3808G01-Q1 | 1.5 | 3 | %VIT | ||
–40°C < TJ < 85°C | 1 | 2 | |||||
1 | 2.5 | ||||||
R MR | MR internal pullup resistance | VSENSE = VIT | 70 | 90 | kΩ | ||
ISENSE | Input current at SENSE pin | TPS3808G01-Q1 | –25 | 25 | nA | ||
VSENSE = 6.5 V | 1.7 | μA | |||||
IOH | RESET leakage current | V RESET = 6.5 V, RESET not asserted | 300 | nA | |||
CIN | Input capacitance, any pin | CT pin | VIN = 0 V to VDD | 5 | pF | ||
Other pins | VIN = 0 V to 6.5 V | 5 | |||||
VIL | MR logic low input | 0 | 0.3 VDD | V | |||
VIH | MR logic high input | 0.7 VDD | VDD | V |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
td | RESET delay time | CT = Open | See Figure 1 | 12 | 20 | 28 | ms |
CT = VDD | 180 | 300 | 420 | ||||
CT = 100 pF | 0.75 | 1.25 | 1.75 | ||||
CT = 180 nF | 0.7 | 1.2 | 1.7 | s | |||
tpHL | Propagation delay | MR to RESET | VIH = 0.7 VDD, VIL = 0.3 VDD | 150 | ns | ||
High-level to low-level RESET delay | SENSE to RESET | VIH = 1.05 VIT, VIL = 0.95 VIT | 20 | μs | |||
tw | Maximum transient duration | SENSE | VIH = 1.05 VIT, VIL = 0.95 VIT | 20 | μs | ||
MR | VIH = 0.7 VDD, VIL = 0.3 VDD | 0.001 |