8.3.1 Immunity to SENSE Pin Voltage Transients

The TPS3808Gxx-Q1 is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage graph (Figure 9). This graph shows the duration that the transient is below V_IT compared to the magnitude of the voltage drop below V_IT, or overdrive voltage. The overdrive voltage is expressed as a percentage of the V_IT threshold value. Any combination of transient duration and overdrive voltage that lies above the curve results in RESET being asserted low. Any transient that lies below the curve is ignored by the device.

Figure 8. Threshold Overdrive Voltage

Figure 9. Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage

8.3.2 SENSE Input

The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin drops below V_IT, RESET is asserted low. The comparator has a built-in hysteresis to ensure smooth RESET assertions and deassertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics.

The TPS3808G01-Q1 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 10.

Figure 10. Using the TPS3808G01-Q1 to Monitor a User-Defined Threshold Voltage

8.3.3 Manual Reset (MR) Input

The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 V_DD) on MR causes RESET to assert low. After MR returns to a logic high and SENSE is above its reset threshold, RESET is deasserted high after the user-defined reset delay expires. MR is internally tied to V_DD using a 90-kΩ resistor, so this pin can be left unconnected if MR is not used.

See Figure 11 for how MR can be used to monitor multiple system voltages. If the logic signal driving MR does not go fully to V_DD, there will be some additional current draw into V_DD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as shown in Figure 12.

Figure 11. Using MR to Monitor Multiple System Voltages

Figure 12. Using an External MOSFET to Minimize I_DD When MR Signal Does Not Go to V_DD

8.3.4 Selecting the Reset Delay Time

The TPS3808Gxx-Q1 device has three options for setting the RESET delay time as shown in Figure 13. Figure 13 (a) shows the configuration for a fixed 300-ms typical delay time by tying C_T to V_DD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 13 (b) shows a fixed 20-ms delay time by leaving the C_T pin open. Figure 13 (c) shows a ground referenced capacitor connected to C_T for a user-defined program time from 1.25 ms to 10 s.

Figure 13. Configuration Used to Set the RESET Delay Time

The capacitor C_T should be ≥100 pF nominal value for the TPS3808Gxx-Q1 to recognize the capacitor is present. Use Equation 1 to calculate the capacitor value for a given delay time.

Equation 1.

The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When RESET asserts low, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET deasserts. A low-leakage type capacitor such as a ceramic should be used and that stray capacitance around this pin may cause errors in the reset delay time.

Table 1. Truth Table