SBVS050M May   2004  – March 2023 TPS3808

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Voltage Thresholds
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET ( MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Switching Characteristics

1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.#SBVS0507773
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
twInput pulse width to RESETSENSEVIH = 1.05 VIT, VIL = 0.95 VIT20μs
MRVIH = 0.7 VDD, VIL = 0.3 VDD0.001
tdRESET delay timeCT = OpenSee #SBVS050FIG7156122028ms
CT = VDD180300420
CT = 100 pF0.751.251.75
CT = 180 nF0.71.21.7s
Propagation delayMR to RESETVIH = 0.7 VDD, VIL = 0.3 VDD150ns
High-to-low level RESET delaySENSE to RESETVIH = 1.05 VIT, VIL = 0.95 VIT20μs
(1) RLRESET and CLRESET are the resistor and capacitor connected to the RESET pin.
GUID-C6886B69-A769-42B1-94CF-D8D60E22F33E-low.gifFigure 7-1 TPS3808 Timing Diagram Showing MR and SENSE Reset Timing