SBVS430B April   2023  – December 2023 TPS3808E-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Voltage Thresholds
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET (MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Modules
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

At 1.7 V ≤ VDD ≤ 6 V, CT = MR =  Open, RESET Voltage (VRESET) = 100 kΩ to VDD, RESET load = 50 pF, and over the operating free-air temperature range of -40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage 1.7 6 V
VDD Supply Voltage 0C to 85C 1.65 6 V
VPOR Power on reset voltage(2) VOL(max) = 0.25 V, IOUT = 15 µA 1 V
VIT-(UV) Negative-going threshold accuracy Fixed threshold TPS3808EG01 -2 ±1 2 %
VIT-(UV) Negative-going threshold accuracy -1.5 ±0.5 1.5 %
VIT-(UV) Negative-going threshold accuracy -40C to 85C -1.25 ±0.5 1.25 %
VHYS Hysteresis Voltage(1) Fixed Vth 1 2.5 %
VHYS Hysteresis Voltage(1) Adjustable Vth 1 2.5 %
VHYS Hysteresis Voltage(1) -40C to 85C 1 2 %
IDD Supply current
VDD = 3.3 V
 		 0.6 1.5 µA
IDD Supply current
VDD = 6 V
 		 0.6 1.5 µA
ISENSE Input current, SENSE pin VSENSE = VIT, TPS3808EG01 -25 25 nA
ISENSE Input current, SENSE pin VSENSE = 6 V, Fixed Versions 0.75 1.25 µA
VOL Low level output voltage 1.3 V ≤ VDD < 1.7 V, IOUT = 0.4 mA 300 mV
VOL Low level output voltage 1.7 V ≤ VDD < 6 V, IOUT = 1 mA 400 mV
ILKG Open drain output leakage current VDD = VRESET  = 6 V 300 nA
VMR_L MR logic low input 0.3 VDD V
VMR_H MR logic high input 0.7 VDD V
RMR Manual reset Internal pullup resistance 90 KΩ
(1) Hysteresis is with respect of the tripoint VIT-(UV).
(2) VPOR is the minimum VDD voltage level for a controlled output state.