SNVSCE0B May   2023  – January 2024 TPS3808E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Voltage Thresholds
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET (MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Modules
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Selecting the RESET Delay Time

The TPS3808E has three options for setting the RESET delay time as shown in Figure 8-4. Figure 8-4 (a) shows the configuration for a fixed 300ms typical delay time by tying CT to VDD; a resistor from 40kΩ to 200kΩ must be used. Supply current is not affected by the choice of resistor. Figure 8-4 (b) shows a fixed 20ms delay time by leaving the CT pin open. Figure 8-4 (c) shows a ground referenced capacitor connected to CT for a user-defined program time between 1.25ms and 10s.

GUID-20230414-SS0I-MXN8-2XVR-8PF2PLQ0VZBK-low.svgFigure 8-4 Configuration Used to Set the RESET Delay Time

The capacitor CT must be ≥ 100pF nominal value for the TPS3808Exxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using Equation 1.

Equation 1. GUID-46382FB9-3E82-4822-8235-2818BCF09B4E-low.gif

The reset delay time is determined by the time it takes an on-chip precision 220nA current source to charge the external capacitor to the internal threshold. When a RESET is asserted, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches higher than the internal threshold, RESET is deasserted. Note that a low-leakage type capacitor such as a ceramic must be used, and that stray capacitance around this pin may cause errors in the reset delay time.