SNVSCE0B May 2023 – January 2024 TPS3808E
PRODUCTION DATA
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3VDD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above the reset threshold, RESET is de-asserted after the user-defined reset delay expires. Note that MR is internally tied to VDD using a 90kΩ resistor, so this pin can be left unconnected if MR is not used.
See Figure 8-5 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to VDD, there is some additional current draw into VDD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 8-6.