SPRS288H May   2008  – October 2021

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Glitch Immunity
      2. 7.3.2 Implemented Window-Watchdog Settings
        1. 7.3.2.1 Timing Rules of Window-Watchdog
      3. 7.3.3 Watchdog Software Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lower-Boundary Calculation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Window-Watchdog Using an External Capacitor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics

RL = 1 MΩ, CL = 50 pF, TA = –40°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td Delay time VDD ≥ VIT + 0.2 V (see Figure 7-3) 20 25 30 ms
tt(out) Watchdog time-out Upper limit WDT = 0 V 0.2 0.25 0.3 s
WDT = VDD 2 2.5 3
WDT = programmable (1) See (2) ms
Watchdog window ratio WDR = 0 V, WDT = 0 V 1:31.8
WDR = 0 V, WDT = VDD 1:32
WDR = 0 V, WDT = programmable 1:25.8
WDR = VDD, WDT = 0 V 1:124.9
WDR = VDD, WDT = VDD 1:127.7
WDR = VDD, WDT = programmable 1:64.5
tPHL Propagation (delay) time, high-to-low-level output VDD to RESET delay VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 30 50 μs
(1) 155 pF < C(ext) < 63 nF
(2) (C(ext) / 15.55 pF + 1) × 6.25 ms