SNVSBA1B April   2019  – April 2020 TPS3840-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: Automotive Off-Battery Monitoring
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves: TPS3840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Detailed Design Procedure

The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840-Q1 from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that when the 12-V rail drops to 7.7 V, the VDD pin for TPS3840-Q1 will be at 1.6 V which is the VIT- threshold for triggering a undervoltage condition for TPS3840DL16-Q1 as shown in Equation 7. Reasonably sized resistors were selected for the voltage divider. While selecting lower resistor values may increase current, this allows for additional accuracy from the resistor divider.

Equation 7. Vrail_trigger = VIT- x (R2 ÷ (R1 + R2))

where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of TPS3840, and R1 and R2 are the top and bottom resistors of the external resistor divider. VIT- is fixed per device variant and is 1.6 V for TPS3840DL16-Q1. Substituting in the values from Figure 50, the undervoltage trigger threshold for the rail is set to 7.7 V. Given that R1 = 100 kΩ, R2 = 26.2 kΩ.

Because the undervoltage trigger of 10 V on the rail corresponds to 1.6 V undervoltage threshold trigger of the TPS3840-Q1 device, there is room for the rail to rise up while maintaining less than 10 V on the VDD pin of the TPS3840-Q1. Equation 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for TPS3840-Q1.

Equation 8. Vrail_max = 10 V x (26.2 kΩ ÷ (100 kΩ + 26.2 kΩ)) = 48.168 V

This means the monitored voltage rail can go as high as 48.168 V and not violate the recommended maximum for the VDD pin on TPS3840-Q1. This is useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail voltage such as in this case. Notice that the resistor values chosen are less than 100kΩ to preserve the accuracy set by the internal resistor divider. Good design practice recommends using a 0.1-µF capacitor on the VDD pin and this capacitance may need to increase when using an external resistor divider.