SNVSBA1B April 2019 – April 2020 TPS3840-Q1
PRODUCTION DATA.
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR with pulse duration longer than tMR_RES will causes reset output to assert. After MR returns to a logic high (VMR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND. VMR must not be higher than VDD voltage.