SNVSBA1B April   2019  – April 2020 TPS3840-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: Automotive Off-Battery Monitoring
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves: TPS3840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted. Typical values are at TJ = 25°C. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup Delay(1) CT pin open 100 220 350 µs
tP_HL Propagation detect delay for VDD falling below VIT- VDD = VIT+ to (VIT-) - 10%(2) 15 30 µs
tD Reset time delay(3) CT pin = open
 		 50 µs
CT pin = 10 nF 6.2 ms
CT pin = 1 µF 619 ms
tGI_VIT- Glitch immunity VIT- 5% VIT- overdrive(4) 10 µs
tMR_PW MR pin pulse duration to initiate reset 300 ns
tMR_RES Propagation delay from MR low to reset VDD = 4.5 V, MR < VMR_L 700 ns
tMR_tD Delay from release MR to deasert reset VDD = 4.5 V,
MR = VMR_L to VMR_H   		tD ms
(1) When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a capacitor at CT pin will add tD delay to tSTRT time
(2) tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants. 
(3) The MIN and MAX reset time delay with external capacitor depends on RCT and is calculated using Equation 5 and Equation 6 in Section 8.3.2
(4) Overdrive % = [(VDD/ VIT-) - 1] × 100%
TPS3840-Q1 TD-TPS3840DL-Rev4.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.
2. Open-Drain timing diagram assumes pull-up resistor is connected to RESET
Figure 4. Timing Diagram TPS3840DL-Q1 (Open-Drain Active-Low)
TPS3840-Q1 TD-TPS3840PL-Rev4.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.
Figure 5. Timing Diagram TPS3840PL-Q1 (Push-Pull Active-Low)
TPS3840-Q1 TD-TPS3840PH-Rev3.gif
1. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.
Figure 6. Timing Diagram TPS3840PH-Q1 (Push-Pull Active-High)