SNVSCK4A April   2024  – August 2024 TPS3842-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
      2. 7.3.2 SENSE Hysteresis
      3. 7.3.3 Selecting the SENSE Delay Time
      4. 7.3.4 Selecting the RESET Delay Time
      5. 7.3.5 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 RESET Output

RESET (active low) denoted with a bar above the pin label. RESET remains high voltage (VOH, deasserted) (open-drain variant VOH is measured against the pullup voltage) as long as sense voltage is in normal operation above the threshold boundary and VDD voltage is above VDD(min). If SENSE falls below VITN for a time period longer than tPD+tCTS, RESET is asserted, driving the RESET pin to a low impedance.

Once SENSE is above VITN + VHYS, a delay circuit (CTR) is enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state.

Open-drain output requires an external pull-up resistor to hold the voltage high to the required voltage logic. Connect the pull-up resistor to the proper voltage rail to enable the output to be connected to other devices at the correct interface voltage levels. RESET supports pull-up voltages up to 42V and is independent of VDD and SENSE voltages.

To select the right pull-up resistor, consider system VOH and the Open-Drain Leakage Current (ILKG) provided in the electrical characteristics to set the maximum pull-up resistor value. Low pull-up resistor values increase the amount of current through the internal open-drain output. The current through the open-drain output must be lower than the IRESET of the device.