SNVSCK4A April   2024  – August 2024 TPS3842-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
      2. 7.3.2 SENSE Hysteresis
      3. 7.3.3 Selecting the SENSE Delay Time
      4. 7.3.4 Selecting the RESET Delay Time
      5. 7.3.5 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPS3842-Q1 high voltage supervisor product family is designed to assert a RESET signal when the SENSE pin voltage drops below VITN and stays below VITN for user defined time. The RESET output remains asserted for a user-adjustable time until after SENSE voltages returns above the respective threshold and hysteresis.

VDD, SENSE and RESET pins can support 42V continuous operation. All VDD, SENSE, and RESET voltage levels can be independent of each other. The TPS3842-Q1 features capacitor programmable sense time delay (CTS) to set a minimum duration of a undervoltage event before RESET is asserted. CTS feature also functions as a programmable de-glitch to avoid false resets. The TPS3842-Q1 also features a capacitor programmable reset time delay (CTR) to set a minimum duration of RESET assertion after a undervoltage event recovers.