SNVSCK5A
April 2024 – August 2024
TPS3842
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specification
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagram
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
SENSE Input
7.3.1.1
SENSE Hysteresis
7.3.2
Selecting the SENSE Delay Time
7.3.3
Selecting the RESET Delay Time
7.3.4
RESET Output
7.4
Device Functional Modes
7.4.1
Normal Operation (VDD > VDD(min))
7.4.2
Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
7.4.3
Below Power-On Reset (VDD < VPOR)
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Meeting the Sense and Reset Delay
8.2.3
Application Curve
8.2.4
Power Supply Recommendations
8.2.5
Layout
8.2.5.1
Layout Guidelines
8.2.5.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Trademarks
9.3
Electrostatic Discharge Caution
9.4
Support Resources
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRL|6
MPDS159H
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snvsck5a_oa
8.2.1
Design Requirements
Table 8-1 Design Parameters
PARAMETER
DESIGN REQUIREMENT
Voltage Threshold
Typical UV voltage threshold 9.5V
Output logic
Open-Drain
SENSE delay
< 0.2ms
RESET
delay
300ms