SNVSCK5A April   2024  – August 2024 TPS3842

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
        1. 7.3.1.1 SENSE Hysteresis
      2. 7.3.2 Selecting the SENSE Delay Time
      3. 7.3.3 Selecting the RESET Delay Time
      4. 7.3.4 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
        2. 8.2.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Support Resources
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 SENSE Input

The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops below VITN for a tPD+tCTS time interval, then RESET is asserted. The comparator has a built-in hysteresis to suppress unintended RESET assertions and de-assertions. For noisy envirionments, good analog design practice is to put a 1nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics or leaverage the CTS feature to set a minimum fault time interval before RESET is asserted.

Figure 7-3 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the 700mV threshold option when using an external resistor divider. The variant bypasses the internal resistor ladder for higher accuracy when using external resistors.

For example, consider a 12V rail, VMON, being monitored for undervoltage (UV) using of the TPS3842A011DRLR variant, as shown in Figure 7-3. The monitored UV threshold, denoted as VMON-, is the desired voltage where the device asserts the reset. For this example VMON- = 5.8V. To assert an undervoltage reset the voltage at the sense pin, VSENSE, needs to be equal to the input threshold negative, VITN. For this example variant VSENSE = VITN = 0.7V. Using R1 and R2 the correlation between VMON- and VSENSE can be seen in Equation 1. Assuming R1 = 100kΩ, and R2 can be calculated as R2 = 13.7kΩ.

Equation 1. VSENSE = VMON- × (R2 ÷ (R1 + R2))

The TPS3842 hysteresis depends on the configuration selected. For the reset signal to become deasserted, VMON must go above VITN + VHYS. For this example variant a 1% voltage threshold hysteresis was selected. Therefore, VMON equals 5.858V when the reset signal becomes deasserted. If a 10% hysteresis option was instead used, VMON equals 6.38V when the reset signal becomes deasserted.

TPS3842 Using the TPS3842A011DRLR to Monitor a User-Defined Threshold VoltageFigure 7-3 Using the TPS3842A011DRLR to Monitor a User-Defined Threshold Voltage