SNVSCK5 April   2024 TPS3842

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
        1. 8.3.1.1 SENSE Hysteresis
      2. 8.3.2 Selecting the SENSE Delay Time
      3. 8.3.3 Selecting the RESET Delay Time
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Meeting the Sense and Reset Delay
      3. 9.2.3 Application Curve
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
        2. 9.2.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Support Resources
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 SENSE Input

The SENSE input provides a pin at which any system voltage can be monitored. If the voltage on this pin drops below VITN for a TPD+TCTS time interval, then RESET is asserted. The comparator has a built-in hysteresis to suppress unintended RESET assertions and de-assertions. For noisy envirionments, good analog design practice is to put a 1nF bypass capacitor on the SENSE input to reduce sensitivity to transients and layout parasitics or leaverage the CTS feature to set a minimum fault time interval before RESET is asserted.

Figure 8-3 illustrates an example of how to adjust the voltage threshold with external resistor dividers. The resistors can be calculated depending on the desired voltage threshold and device part number. TI recommends using the 700mV threshold option when using an external resistor divider. The variant bypasses the internal resistor ladder for higher accuracy when using external resistors.

For example, consider a 12V rail, VMON, being monitored for undervoltage (UV) using of the TPS3842A011DRLR variant, as shown in Figure 8-3. The monitored UV threshold, denoted as VMON-, is the desired voltage where the device asserts the reset. For this example VMON- = 5.8V. To assert an undervoltage reset the voltage at the sense pin, VSENSE, needs to be equal to the input threshold negative, VITN. For this example variant VSENSE = VITN = 0.7V. Using R1 and R2 the correlation between VMON- and VSENSE can be seen in Equation 1. Assuming R2 = 100kΩ, and R1 can be calculated as R1 = 16kΩ.

Equation 1. VSENSE = VMON- × (R2 ÷ (R1 + R2))

The TPS3842 hysteresis depends on the configuration selected. For the reset signal to become deasserted, VMON must go above VITN + VHYS. For this example variant a 1% voltage threshold hysteresis was selected. Therefore, VMON equals 5.858V when the reset signal becomes deasserted. If a 10% hysteresis option was instead used, VMON equals 6.38V when the reset signal becomes deasserted.

There are inaccuracies that must be taken into consideration while adjusting voltage thresholds. Aside from the tolerance of the resistor divider, there is an internal resistance of the SENSE pin that can affect the accuracy of the resistor divider. Although expected to be very high impedance, users are recommended to calculate the values for the design specifications. The internal SENSE resistance (RSENSE) can be calculated by the SENSE voltage (VSENSE) divided by the SENSE current (ISENSE) as shown in Equation 3. VSENSE can be calculated using Equation 1 depending on the resistor divider and monitored voltage. ISENSE can be calculated using Equation 2.

Equation 2. ISENSE = [(VMON - VSENSE) ÷ R1] - (VSENSE ÷ R2)
Equation 3. RSENSE = VSENSE ÷ ISENSE
GUID-20240301-SS0I-HBT1-3VPH-7XDDFWTCT4BD-low.svg Figure 8-3 Using the TPS3842A011DRLR to Monitor a User-Defined Threshold Voltage