SNVSCK5A April   2024  – August 2024 TPS3842

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 SENSE Input
        1. 7.3.1.1 SENSE Hysteresis
      2. 7.3.2 Selecting the SENSE Delay Time
      3. 7.3.3 Selecting the RESET Delay Time
      4. 7.3.4 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Meeting the Sense and Reset Delay
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
        2. 8.2.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Trademarks
    3. 9.3 Electrostatic Discharge Caution
    4. 9.4 Support Resources
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Selecting the RESET Delay Time

TPS3842 has adjustable reset release time delay with external capacitors.

  • A capacitor on CTR programs the reset time delay of the output.
  • No capacitor on this pin gives the fastest reset delay time.
  • Parasitic capacitance on the CTR pin counts as CTR capacitance and increases tCTR.

The time delay (tCTR) can be programmed by connecting a capacitor between CTR pin and GND.

The relationship between external capacitor CCTR_EXT (typ) and the time delay tCTR (typ) is given by Equation 5.

Equation 5. tCTR (typ) = 2.858 x CCTR_EXT (typ)

tCTR (typ) = is given in seconds (s)

CCTR_EXT (typ) = is given in microfarads (μF)

The reset delay varies according to the external capacitor (CCTR_EXT). The minimum and maximum variance due to the constant is show in Equation 6 and Equation 7:

Equation 6. tCTR (max) = 3.715 x CCTR_EXT (max)
Equation 7. tCTR (min) = 2 x CCTR_EXT (min)

Having a too large of a capacitor value (>10µF) can cause very slow charge up (rise times) due to capacitor leakage and system noise can cause the internal circuit to hold RESET active.

* Leakages on the capacitor can effect accuracy of reset time delay.