SNVSCK5
April 2024
TPS3842
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specification
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagram
7
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
SENSE Input
8.3.1.1
SENSE Hysteresis
8.3.2
Selecting the SENSE Delay Time
8.3.3
Selecting the RESET Delay Time
8.3.4
RESET Output
8.4
Device Functional Modes
8.4.1
Normal Operation (VDD > VDD(min))
8.4.2
Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
8.4.3
Below Power-On Reset (VDD < VPOR)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Meeting the Sense and Reset Delay
9.2.3
Application Curve
9.2.4
Power Supply Recommendations
9.2.5
Layout
9.2.5.1
Layout Guidelines
9.2.5.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Trademarks
10.3
Electrostatic Discharge Caution
10.4
Support Resources
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DRL|6
MPDS159G
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snvsck5_oa
1
Features
Wide supply voltage range: 1.9V to 42V
VDD, SENSE, and
RESET
are rated to 42V
Low quiescent current: 850nA (typical)
High threshold accuracy: 0.5% (typical)
Fixed internal threshold voltages: 2.7V to 9.5V
Adjustable voltage variant: 0.7V
Capacitor programmable adjustable delay time with CTR pin
Capacitor programmable deglitch delay time with CTS pin
Open-drain, active-low output
Temperature range: –40°C to 125°C
Small size: SOT563 (DRL)