SNVSCK5 April   2024 TPS3842

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
        1. 8.3.1.1 SENSE Hysteresis
      2. 8.3.2 Selecting the SENSE Delay Time
      3. 8.3.3 Selecting the RESET Delay Time
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Meeting the Sense and Reset Delay
      3. 9.2.3 Application Curve
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
        2. 9.2.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Support Resources
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

At 1.9V ≤ VDD ≤ 42V, CTS = CTR = Open, RESET Voltage (VRESET) = 100kΩ to VDD, RESET load = 50pF, and over the operating free-air temperature range of –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply Voltage 1.9 42 V
VPOR Power on reset voltage(2) VOL(max) = 0.25V, IOUT = 15µA 1.4 V
VITN Negative-going threshold accuracy Fixed internal threshold, VITN = 2.7V to 9.5V -1.5 ±0.5 1.5 %
VITN Negative-going threshold accuracy Adjustable internal threshold, VITN = 700mV -1.5 ±0.5 1.5 %
VHYS Hysteresis Voltage(1) 1% Variant 0.5 1 1.5 %
VHYS Hysteresis Voltage(1) 5% Variant 4.5 5 5.5 %
VHYS Hysteresis Voltage(1) 10% Variant 9.5 10 10.5 %
IDD Supply current VDD = 12V, RESET = Not asserted 0.85 2.1 µA
ISENSE Input current, SENSE pin VSENSE = VITN, Adjustable version -25 25 nA
ISENSE Input current, SENSE pin VSENSE = 12V, Fixed versions 1.35 2.5 µA
VOL Low level output voltage 1.9V ≤ VDD < 42V, IOUT = 0.5mA 400 mV
ILKG Open drain output leakage current VDD = VRESET  = 12V 300 nA
(1) Hysteresis is with respect of the tripoint VITN.
(2) VPOR is the minimum VDD voltage level for a controlled output state.