SBVS264B January 2017 – September 2021 TPS3850-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Reset delay | Minimum reset delay of 250 ms | Minimum reset delay of 260 ms, reset delay of 322 ms (typical) |
Watchdog window | Functions with a 200-Hz pulse-width modulation (PWM) signal with a 50% duty cycle | Leaving the CWD pin unconnected with SET0 = 0 and SET1 = 1 produces a window with a tWDL(max) of 2.2 ms and a tWDU(min) of 22 ms |
Output logic voltage | 1.8-V CMOS | 1.8-V CMOS |
Monitored rail | 1.2 V within ±5% | Worst-case VIT+(OV) 1.257 V (4.8%) |
Worst-case VIT-(UV) 1.142 V (4.7%) | ||
Maximum device current consumption | 200 µA | 10 µA of current consumption, typical worst-case of 199 µA when WDO or RESET is asserted |