SBVS285 February 2017 TPS3852-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Watchdog disable for initialization period | Watchdog must remain disabled for 7 seconds until logic enables the watchdog timer | 7.21 seconds (typ) |
Output logic voltage | 3.3-V CMOS | 3.3-V CMOS |
Monitored rail | 3.3 V with a 5% threshold | Worst-case VITN = 3.142 V (–4.7% threshold) |
Watchdog window | 250 ms, maximum | tWDL(max) = 135 ms, tWDU(min) = 181 ms |
Maximum device current consumption | 50 µA | 52 µA (worst-case) when RESET or WDO is asserted(1) |