SBVS285 February   2017 TPS3852-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      Undervoltage Threshold (VITN) Accuracy vs Temperature
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 RESET
      2. 7.3.2 Manual Reset (MR)
      3. 7.3.3 Undervoltage Fault Detection
      4. 7.3.4 Watchdog Mode
        1. 7.3.4.1 SET1
        2. 7.3.4.2 Window Watchdog Timer
        3. 7.3.4.3 Watchdog Input (WDI)
        4. 7.3.4.4 CWD
        5. 7.3.4.5 Watchdog Output (WDO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 VDD is Below VPOR (VDD < VPOR)
      2. 7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min))
      3. 7.4.3 Normal Operation (VDD ≥ VDD(min))
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 CWD Functionality
        1. 8.1.1.1 Factory-Programmed Timing Options
        2. 8.1.1.2 Adjustable Capacitor Timing
      2. 8.1.2 Overdrive Voltage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Monitoring the 3.3-V Rail
        2. 8.2.2.2 Calculating RESET and the WDO Pullup Resistor
        3. 8.2.2.3 Setting the Window Watchdog
        4. 8.2.2.4 Watchdog Disabled During Initialization Period
      3. 8.2.3 Glitch Immunity
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Module
      2. 11.1.2 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ +125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
MINTYPMAXUNIT
GENERAL
tINIT CWD pin evaluation period 381 µs
Minimum MR, SET1 pin pulse duration 1 µs
Startup delay 300 µs
RESET FUNCTION
tRST Reset timeout period 170 200 230 ms
tRST-DEL VDD to RESET delay VDD = VITN + VHYST + 2.5% 35 µs
VDD = VITN – 2.5% 17
tMR-DEL MR to RESET delay 200 ns
Watchdog Function
tWDL Window watchdog lower boundary CWD = NC, SET1 = 0(1) Watchdog disabled
CWD = NC, SET1 = 1(1) 680 800 920 ms
CWD = 10 kΩ to VDD,
SET1 = 0(1)		 Watchdog disabled
CWD = 10 kΩ to VDD,
SET1 = 1(1)		 1.48 1.85 2.22 ms
tWDU Window watchdog upper boundary CWD = NC, SET1 = 0(1) Watchdog disabled
CWD = NC, SET1 = 1(1) 1360 1600 1840 ms
CWD = 10 kΩ to VDD,
SET1 = 0(1)		 Watchdog disabled
CWD = 10 kΩ to VDD,
SET1 = 1(1)		 9.35 11.0 12.65 ms
tWD-setup Setup time required for device to respond to changes on WDI after being enabled 150 µs
Minimum WDI pulse duration 50 ns
tWD-DEL WDI to WDO delay 50 ns
(1) SET1 = 0 means VSET1 < VIL, SET1 = 1 means VSET1 > VIH.
TPS3852-Q1 WD_Timing.gif
1. See Figure 2 for WDI timing requirements.
Figure 1. Timing Diagram
TPS3852-Q1 Min_Max_Timing.gifFigure 2. TPS3852-Q1 Window Watchdog Timing