The TPS3852 is a precision voltage supervisor with an integrated window watchdog timer. The TPS3852 includes a precision undervoltage supervisor with an undervoltage threshold (VITN) that achieves 0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3852 includes accurate hysteresis making the device ideal for use with tight tolerance systems. The supervisor RESET delay features a 15% accuracy, high-precision delay timer.
The TPS3852 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output (WDO) enables increased resolution to help determine the nature of fault conditions. The watchdog timeouts can be programmed either by an external capacitor, or by factory-programmed default delay settings. The watchdog can be disabled to avoid undesired watchdog timeouts during the development process.
The TPS3852 is available in a small 3.00-mm × 3.00-mm, 8-pin VSON package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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TPS3852 | VSON (8) | 3.00 mm × 3.00 mm |
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DATE | REVISION | NOTES |
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November 2016 | * | Initial release. |
NAME | NO. | I/O | DESCRIPTION |
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CWD | 2 | — | Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table. When using a capacitor, the TPS3852 determines the window watchdog upper boundary with Equation 1. See Table 3 and the CWD Functionality section for additional information. |
GND | 4 | — | Ground pin |
MR | 3 | I | Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD. RESET remains low for a fixed reset delay (tRST) time after MR is deasserted (high). |
RESET | 8 | O | Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the RESET timeout-counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the monitored voltage is within the correct operating range (above VITN+VHYST) and the RESET timeout is complete. |
SET1 | 5 | I | Logic input. Grounding the SET1 pin disables the watchdog timer. |
VDD | 1 | I | Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended. |
WDI | 6 | I | Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min)) window boundaries in order for WDO to not assert. When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND. |
WDO | 7 | O | Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-impedance state. |
Thermal pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |