SBVS105F September   2009  – October 2018 TPS386000 , TPS386040

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPS386000 Typical Application Circuit: Monitoring Supplies for an FPGA
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Watchdog Timer
      4. 8.3.4 Reset Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
      2. 9.1.2 Undervoltage and Overvoltage Detection
      3. 9.1.3 Sensing a Negative Voltage
      4. 9.1.4 Reset Delay Time
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1 Design Requirements

This design is intended to monitor the voltage rails for an FPGA. Table 7 summarizes the design requirements.

Table 7. Design Requirements

PARAMETER DESIGN REQUIREMENT
VDD 5 V
VMON(1) 1.8 V –5%
VMON(2) 1.5 V –5%
VMON(3) 1.2 V –5%
VMON(4) 1 V ±5%
Approximate start-up time 100 ms