SNVSC27A October   2022  – November 2022 TPS38700

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

At 2 V ≤ VDD ≤ 5.5 V, NIRQ/NRST Voltage  = 10 kΩ to VDD, NIRQ/NRST load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD = 3.3 V.
MIN NOM MAX UNIT
Common parameters
tD_ENx ENx toggle delay from start of time slot From start of time slot 10 µs
tD_CLK32K CLK32K toggle delay from start of time slot From start of time slot 10 µs
F_CLK32K Frequency Capacitive load = 12pF 32768 Hz
D_CLK32K Duty cycle Capacitive load = 12pF 40 50 60 %
Trf_CLK32K Rise and fall time of CLK32K (Rpullup = 4.7 kΩ) Capacitive load = 12pF 50 ns
tD_ENx,y Delay between 2 subsequent EN in same time slot 1 µs
tNRST_EN ENx delay from NRST in Emergency Shutdown Sequence 2 and 9 200 ns
tD_NRST NRST assertion latency from falling edge of ACT pin below VIL or falling edge of VDD pin below VDDmin 25 µs
tD_NIRQ Fault detection to NIRQ assertion latency 25 µs
tBIST POR to ready with BIST including OTP load with ECC 15 ms
tNo_BIST POR to ready without BIST including OTP load with ECC 2.5 ms
BIST time 12.5 ms
tStartup_CLK32K Clock 32k startup from UVLO at power ON 50 ms
Freq_fault Crystal frequency fault detection time 1 ms
I2C Timing Characteristics
fSCL Serial clock frequency (1) Standard mode 100 kHz
fSCL Serial clock frequency (1) Fast mode 400 kHz
fSCL Serial clock frequency (1) Fast mode + 1 MHz
tLOW SCL low time (1) Standard mode 4.7 µs
tLOW SCL low time (1) Fast mode 1.3 µs
tLOW SCL low time (1) Fast mode + 0.5 µs
tHIGH SCL high time (1) Standard mode 4 µs
tHIGH SCL high time (1) Fast Mode 1 µs
tHIGH SCL high time (1) Fast mode + 0.26 µs
tSU_DAT Data setup time (1) Standard mode 250 ns
tSU_DAT Data setup time (1) Fast mode 100 ns
tSU_DAT Data setup time (1) Fast mode + 50 ns
tHD_DAT Data hold time (1) Standard mode 10 3450 ns
tHD_DAT Data hold time (1) Fast mode 10 900 ns
tHD_DAT Data hold time (1) Fast mode + 10 ns
tSU_STA Setup time for a Start or Repeated Start condition (1) Standard mode 4.7 µs
tSU_STA Setup time for a Start or Repeated Start condition (1) Fast mode 0.6 µs
tSU_STA Setup time for a Start or Repeated Start condition (1) Fast mode + 0.26 µs
tHD_STA Hold time for a Start or Repeated Start condition (1) Standard mode 4 µs
tHD_STA Hold time for a Start or Repeated Start condition (1) Fast mode 0.6 µs
tHD_STA Hold time for a Start or Repeated Start condition (1) Fast mode + 0.26 µs
tBUF Bus free time between a STOP and START condition (1) Standard mode 4.7 µs
tBUF Bus free time between a STOP and START condition (1) Fast mode 1.3 µs
tBUF Bus free time between a STOP and START condition (1) Fast mode + 0.5 µs
tSU_STO Setup time for a Stop condition (1) Standard mode 4 µs
tSU_STO Setup time for a Stop condition (1) Fast mode 0.6 µs
tSU_STO Setup time for a Stop condition (1) Fast mode + 0.26 µs
trDA Rise time of SDA signal (1) Standard mode 1000
trDA Rise time of SDA signal (1) Fast mode 20 300 ns
trDA Rise time of SDA signal (1) Fast mode + 120 ns
tfDA Fall time of SDA signal (1) Standard mode 300 ns
tfDA Fall time of SDA signal (1) Fast mode 1.4 300 ns
tfDA Fall time of SDA signal (1) Fast mode + 6.5 120 ns
trCL Rise time of SCL signal (1) Standard mode 1000 ns
trCL Rise time of SCL signal (1) Fast mode 20 300 ns
trCL Rise time of SCL signal (1) Fast mode + 120 ns
tfCL Fall time of SCL signal (1) Standard mode 300 ns
tfCL Fall time of SCL signal (1) Fast mode 6.5 300 ns
tfCL Fall time of SCL signal (1) Fast mode + 6.5 120 ns
tSP Pulse width of SCL and SDA spikes that are suppressed (1) Standard mode, Fast mode and Fast mode + 50 ns
(1) Guaranteed by design