SNVSCG1 july   2023 TPS38700S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Sync Functionality
      3. 8.3.3 Transitioning Sequences
        1. 8.3.3.1 Power Up
        2. 8.3.3.2 Power Down
        3. 8.3.3.3 Emergency Power Down
      4. 8.3.4 BACKUP State
      5. 8.3.5 Thermal Shutdown (TSD) State
      6. 8.3.6 I2C
        1. 8.3.6.1 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Test Implementation
      5. 9.2.5 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Application Information

Modern SOC and FPGA devices typically need multiple power rails to provide power to the different blocks within the respective SOC or FPGA. Accurate voltage level and timing requirements are common and must be met to maintain proper operation of these devices. By utilizing TPS38700S-Q1 along with a multichannel voltage supervisor like the TPS389006-Q1, the power up and power down sequencing requirements as well as the core voltage requirements of the target SOC or FPGA can be met. This design can also assist in meeting the strict timing requirements for an SOC or FPGA .