SNVSCG1 july   2023 TPS38700S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Sync Functionality
      3. 8.3.3 Transitioning Sequences
        1. 8.3.3.1 Power Up
        2. 8.3.3.2 Power Down
        3. 8.3.3.3 Emergency Power Down
      4. 8.3.4 BACKUP State
      5. 8.3.5 Thermal Shutdown (TSD) State
      6. 8.3.6 I2C
        1. 8.3.6.1 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Test Implementation
      5. 9.2.5 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.4 Test Implementation

The TPS38700S-Q1 SYNC feature can be demonstrated in a simple test setup with the TPS389006-Q1. For this test, you need the TPS38700Q1EVM-Q1 and the TPS389006Q1EVM-Q1. Replace U1 on the TPS38700Q1EVM with the orderable part TPS38700603SRGERQ1. Replace the U1 on TPS389006Q1EVM with orderable part TPS38900603NRTERQ1. The orderable part TPS38900603NRTERQ1 has initial conditions set such that TPS38700603SRGERQ1 enable voltages meet the UV thresholds to trigger SYNC pulses by default. Connect the system as shown in Figure 9-12. Connect ACT and VDD to two separate power supplies. Configure the settings over I2C as needed. However, note that power cycling the evaluation modules sets the conditions back to default. If you enable ACT and have done everything correctly, then no LED's should be turned on. If something goes wrong, then either NIRQ on TPS389006-Q1 or NRST on TPS38700S-Q1 will be set low.

GUID-20230526-SS0I-80MG-1VVN-HGK945KKL2D0-low.svgFigure 9-2 TPS38700S SYNC Test Implementation

Toggling high ACT makes the waveform of the enable voltages look like Figure 9-3 If the waveform does not look that, then to debug check and make sure that everything is connected properly. If the system is connected properly, then verify the I2C address values are what you expect the values to be. For example check if the status register of MON1 of TPS389006007-Q1 reads the TPS38700S-Q1 EN voltage output in the Fusion Digital Power Tool.

GUID-20230531-SS0I-RTZN-XV0L-3VWS8HJDNCCV-low.svgFigure 9-3 TPS38700S SYNC Sequence Up Test Implementation Waveform

Figure 9-3 shows how the device behaves when ACT is toggled off. Note that there's no delay between when the system detects the ACT falling edge and when NRST and EN6 start sequencing down.

GUID-20230531-SS0I-3Q6B-HKNT-2LD7VZVCTP5H-low.svgFigure 9-4 TPS38700S SYNC Sequence Down Test Implementation Waveform