SNVSCG1 july 2023 TPS38700S-Q1
PRODUCTION DATA
Refer to Table 8-1 for the I2C register map overview. Note that "PSEQ" refers to TPS38700S-Q1 and is used enhance table readability.
| TYPE | BITS | DESCRIPTION | RANGE / FUNCTION OR STATUS | WHO TOGGLES THEM? | WHO ELSE CAN WRITE TO THEM? | WHAT GETS AFFECTED DUE TO THIS BIT? |
|---|---|---|---|---|---|---|
| OTP bits R | VENDORID[7:0] | TI defined | TI defined | OTP option | None | None |
| MODEL_REV[7:0] | TI defined | TI defined | OTP option | None | None | |
| TARGET_ID[7:0] | TI defined | TI defined | OTP option | None | I2C | |
| Interrupt info bits RW1C | F_INTERR | Internal fault | No internal fault / Internal fault detected | Interrupt | Any of the interrupts generated; Can be cleared by writing 1 | NIRQ |
| EM_PD (1) | Emergency Power down | No emergency PD / shutdown caused by emergency PD | PSEQ | PSEQ; SOC | NRST; NIRQ | |
| F_EN | Enable output pin fault | No faults detected / fault detected | EN readback-PSEQ | PSEQ; SOC | NIRQ; NRST | |
| F_NRSTIRQ | Reset or Interrupt pin fault | No faults detected / fault detected | Reset readback-PSEQ | PSEQ; SOC | NIRQ | |
| F_LDO | LDO fault | No faults detected / fault detected | BIST | BIST; SOC | NIRQ; NRST | |
| F_TSD | Thermal shutdown fault | No faults detected / fault detected | TSD | TSD; SOC | NIRQ; NRST | |
| F_RT_CRC | Runtime CRC register fault | No faults detected / fault detected | CRC | SOC | NIRQ | |
| Status bits R | ST_NIRQ | Current state of NIRQ output | NIRQ asserted / not asserted | Interrupt | None | None |
| ST_NRST | Current state of NRST output | NRST asserted / not asserted | Interrupt; NRSTstate change | None | None | |
| ST_ACTSHDN | Current state of ACT input | ACT pin driven Low or High | PSEQ | None | None | |
| ST_PSEQ[1:0] | Current state of PSEQ | SHDNx, Power Up, Power Down, invalid, Active | PSEQ | None | None | |
| STDR1 | Current drive state of GPO12 to GPO9 | Sequencer is driving EN Low or High | PSEQ | None | None | |
| STDR2 | Current drive state of GPO7,8 to EN1 | Sequencer is driving EN Low or High | PSEQ | None | None | |
| CONTROL R/W | FORCE_INT | Force NIRQ low | NIRQ contolled by faults / register | SOC | SOC | NRST |
| FORCE_ACT | Force PSEQ Active state | PSEQ | SOC can clear it; but not set it | PSEQ | ||
| RST_DLY[3:0] | Reset Delay | 0.1 ms to 128 ms | SOC | None | PSEQ | |
| PSEQ | USLOT[3:0] | Power Up time slots | 125 μs / 2.5 s | SOC | None | PSEQ |
| DSLOT[3:0] | Power Down time slots | 125 μs / 2.5 s | SOC | None | PSEQ | |
| SSTEP | Slot step multiplier | 250 μs / 1000 μs | SOC | None | PSEQ | |
| PU[3:0][12:1] | Power Up Sequence | ENx not mapped / ENx mapped | SOC | None | PSEQ | |
| PD[3:0][12:1] | Power Down Sequence | ENx not mapped / ENx mapped | SOC | None | PSEQ | |
| PROT | WRK | Work set register lock | 0 / 1 | SOC only 1 | None | Write function to those register groups |
| SEQS | SEQS set register lock | 0 / 1 | SOC only 1 | None | Write function to those register groups | |
| SEQP | SEQP set register lock | 0 / 1 | SOC only 1 | None | Write function to those register groups | |
| SEQC | SEQC set register lock | 0 / 1 | SOC only 1 | None | Write function to those register groups | |
| CTL | CTL set register lock | 0 / 1 | SOC only 1 | None | Write function to those reg groups |