SNVSCG1 july 2023 TPS38700S-Q1
PRODUCTION DATA
Address: 0x10
Description: Interrupt Source register. If F_INTERNAL, then INT_SRC2 register provides further information.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
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BIT | NAME | DESCRIPTION |
---|---|---|
7 | F_INTERNAL | Internal Fault (ORed value of all bits in INT_SRC2): 0 = No internal fault detected 1 = Internal fault detected. Further detail flagged in INT_SRC2. This bit is cleared by clearing the bits in INT_SRC2. |
6 | EM_PD | Emergency Power Down: 0 = No emergency power-down event 1 = Shutdown caused by emergency power-down (Sequence 2). Write-1-to-clear will clear the bit. The bit will be set again on next emergency power-down. |
3 | RSVD | RSVD |
2 | F_EN | Enable Output Pin Fault: 0 = No short to supply or ground detected. 1 = Short to supply or ground detected. Write-1-to-clear will clear the bit only if the fault condition is also removed. |
1 | RSVD | RSVD |
0 | F_NRSTIRQ | Reset or Interrupt Pin Fault: 0 = No fault detected on NRST or NIRQ. 1 = Low resistance path to supply detected on either NRST or NIRQ. Write-1-to-clear will clear the bit only if the fault condition is also removed. |
INT_SRC1 represents the reason that NIRQ was asserted. When the host processor receives NIRQ, it may read this register to quickly determine the source of the interrupt. If this register is clear, then TPS38700S-Q1 did not assert NIRQ.
Address: 0x11
Description: Interrupt Source register for internal errors.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
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BIT | NAME | DESCRIPTION |
---|---|---|
7 | F_VENDOR | Vendor specific internal fault. Details reported in INT_VENDOR. This bit represents the ORed value of all bits in INT_VENDOR. 0 = No fault reported in INT_VENDOR 1 = Fault reported in INT_VENDOR This bit is cleared by clearing the bits in INT_VENDOR. |
6 | RSVD | Reserved |
5 | F_RT_CRC | Runtime register CRC Fault: 0 = No fault detected. 1 = Register CRC fault detected. Write-1-to-clear will clear the bit. The bit will be set again during next register CRC check if a fault is detected. |
3 | F_LDO | LDO Fault: 0 = No LDO fault detected. 1 = LDO fault detected. If internal LDO is used, this flag is to indicate fault. If internal LDO is not used, this flag must be reserved. Write-1-to-clear will clear the bit only if the fault condition is also removed. |
2 | F_TSD | Thermal Shutdown: 0 = No thermal shutdown. 1 = Thermal shutdown occurred since last read. Write-1-to-clear will clear the bit only if the fault condition is also removed. |
Address: 0x12
Description: Vendor Specific Internal Interrupt Status register.
POR Value: 0x00
Access: Read and write 1 to clear. Writing 0 has no effect; writing 1 to a bit which is already at 0 has no effect.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | FAULTS[7:0] | Vendor specific internal faults flags. |
Address: 0x13
Description: TPS38700S-Q1 Status register for control pins and internal state.
POR Value: 0x00
Access: Read only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:6 | RSVD | Reserved |
5 | ST_NIRQ | Current state of NIRQ Output: 0 = NIRQ pin asserted low by TPS38700S-Q1. 1 = NIRQ pin not asserted low by TPS38700S-Q1. |
4 | ST_NRST | Current state of NRST Output: 0 = NRST pin asserted low by TPS38700S-Q1. 1 = NRST pin not asserted low by TPS38700S-Q1. |
3 | RSVD | RSVD |
2 | ST_ACTSHDN | Current state of ACT input: 0 = ACT pin driven low (Shutdown) by system. 1 = ACT pin driven high (Active) by system. |
1:0 | ST_PSEQ[1:0] | 00b: SHDNx, Power Up, Power Down 01b: NA 10b: Invalid combination 11b: ACTIVE |
Address: 0x14
Description: Current drive status of Enable Pins.
POR Value: 0x00
Access: Read only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:4 | RSVD | Reserved |
3:0 | STDR_GPO[12:9] | Current drive state of GPO[X]: 0 = TPS38700S-Q1 is driving GPO[X] Low. 1 = TPS38700S-Q1 is driving or allowing to float GPO[X] High. |
Address: 0x15
Description: Current drive status of Enable Pins.
POR Value: 0x00
Access: Read only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | STDR_EN[6:1] GPO[8:7] | Current drive state of GPO[X]: 0 = TPS38700S-Q1 is driving GPO[X] Low. 1 = TPS38700S-Q1 is driving or allowing to float GPO[X] High. |
Address: 0x16
Description: Current read status of Enable Pins.
POR Value: 0x00
Access: Read only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:4 | RSVD | Reserved |
3:0 | STRD_GPO[12:9] | Current read state of GPO[X]: 0 = TPS38700S-Q1 is reading GPO[X] Low. 1 = TPS38700S-Q1 is reading GPO[X] High. |
Address: 0x17
Description: Current read status of Enable Pins.
POR Value: 0x00
Access: Read only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | STRD_EN[6:1] GPO[8:7] | Current read state of GPO[X]: 0 = TPS38700S-Q1 is reading GPO[X] Low. 1 = TPS38700S-Q1 is reading GPO[X] High. |
Address: 0x1A
Description: Reason of last NRST assertion or shutdown. NRST assertion and shutdown occur in Sequence 2 and Sequence 3.
The register is maintained as long as VDD and/or VBBAT is present. An emergency shutdown triggering Sequence 2 is already recorded in INT_SRC1.EM_PD register bit, so it does not need to be stored in this register. The host is expected to read this register as part of the first actions taken upon power ON.
The register is overwritten with new relevant data on next NRST assertion or shutdown.
POR Value: 0x00
Access: Read Only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7 | RSVD | Reserved |
5 | RSVD | Reserved |
3 | ACTSHDN | NRST/Shutdown due to ACT asserted Low (shutdown). 0 = Last NRST/Shutdown assertion was not due to ACT Low. 1 = Last NRST/Shutdown assertion was due to ACT Low. |
1 | RSVD | Reserved |
0 |
RSVD |
Reserved |
Address: 0x25
Description: Set General Purpose Output state for sequencing pins EN[12:9]. GPO is enabled through AF_IN_OUT and EN_ALT_F registers.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:4 | RSVD | Reserved |
3 | GPO12 | GPO12 General Purpose Output. Only used when PWR_EN12 is cleared. 0 = GPO12 pin driven low. 1 = GPO12 pin driven high. |
2 | GPO11 | GPO11 General Purpose Output. Only used when PWR_EN11 is cleared. 0 = GPO11 pin driven low. 1 = GPO11 pin driven high. |
1 | GPO10 | EN10 General Purpose Output. Only used when PWR_EN10 is cleared. 0 = EN10 pin driven low. 1 = EN10 pin driven high. |
0 | GPO9 | GPO9 General Purpose Output. Only used when PWR_EN9 is cleared. 0 = GPO9 pin driven low. 1 = GPO9 pin driven high. |
Address: 0x28
Description: Interrupt and State SW control.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:4 | RSVD | Reserved |
3 | FORCE_INT (1) | Force NIRQ low: 0 = NIRQ pin controlled by INT_SRCx register faults. 1 = NIRQ pin forced low. |
Address: 0x29
Description: Miscellaneous configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if CTL group is protected.
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BIT | NAME | DESCRIPTION | |
---|---|---|---|
7:4 | RST_DLY[3:0] | Power up sequence: NRST remains asserted until RST_DLY[3:0] after last ENx assert. | |
0000b = 0.1 ms 0001b = 0.2 ms 0010b = 0.4 ms 0011b = 0.8 ms 0100b = 1.6 ms 0101b = 3.2 ms 0110b = 6.4 ms 0111b = 12.8 ms | 1000b = 1 ms 1001b = 2 ms 1010b = 4 ms 1011b = 8 ms 1100b = 16 ms 1101b = 32 ms 1110b = 64 ms 1111b = 128 ms | ||
Power down sequence: NRST asserted within tNRST of ACT= Low. | |||
3:2 | RSVD | RSVD |
Address: 0x2B
Description: Vendor Specific Internal Interrupt Enable register.
POR Value: 0x00 or load from NVM.
Access: Read/Write. Read-only if CTL group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | FAULTS[7:0] | Vendor specific internal faults enables. |
Address: 0x30
Description: Sequencing configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:1 | RSVD | Reserved |
0 | SSTEP | Sequencing time slot step size selection for SEQ_USLOT and SEQ_DSLOT: 0 = Time slot step size tSSTEP = 250 μs 1 = Time slot step size tSSTEP= 1000 μs |
Address: 0x31
Description: Power Up sequencing time slot configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read only if SEQ group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | TIME[7:0] | Sets time slot between sequencing points on power-up: tUSLOT = SEQ_USLOT.TIME[7:0] × tSSTEP + tSMIN with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2 For the case where SEQ_CFG.SSTEP = 0, refer to Table 8-18. For the case where SEQ_CFG.SSTEP = 1, refer to Table 8-19. |
PARAMETER | SYMBOL | MIN (-6%) | TYPICAL | MAX (+6%) | UNIT |
---|---|---|---|---|---|
Slot step size | tSSTEP | 235 | 250 | 265 | μs |
Min slot time (0x00) | tSMIN | 117.5 | 125 | 132.5 | μs |
Max slot time (0xFF) | tSMAX | 60042.5 | 63875 | 67707.5 | μs |
PARAMETER | SYMBOL | MIN (-6%) | TYPICAL | MAX (+6%) | UNIT |
---|---|---|---|---|---|
Slot step size | tSSTEP | 940 | 1000 | 1060 | μs |
Min slot time (0x00) | tSMIN | 470 | 500 | 530 | μs |
Max slot time (0xFF) | tSMAX | 240170 | 255500 | 270830 | μs |
Address: 0x32
Description: Power Down sequencing time slot configuration.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:0 | TIME[7:0] | Sets time slot between sequencing points on power-down: tDSLOT = SEQ_DSLOT.TIME[7:0] × tSSTEP + tSMIN with tSSTEP set by SEQ_CFG.SSTEP and tSMIN = tSSTEP/2 See Table 8-17 for setting details. |
Address: PWR_EN1 (0x33) - PWR_EN12 (0x3E) (Twelve 8-bit registers).
Description: Power Up/ Down sequence definition by assignment of EN[12:1] to one of fifteen time slots.
Slot=1 is the earliest slot that can be selected and it indicates that the ENx pin will toggle in the first SEQ_USLOT.TIME or SEQ_DSLOT.TIME after the triggering event.
POR Value: Loaded from NVM.
Access: Read/Write. Read-only if SEQ group is protected.
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BIT | NAME | DESCRIPTION |
---|---|---|
7:4 | PU[3:0] | Power Up Sequence: 0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states). 1 = ENx pin mapped to first time slot (first up). 15 = ENx pin mapped to last time slot (last up). |
3:0 | PD[3:0] | Power Down Sequence: 0 = ENx pin not mapped to sequence. ENx maintains previous state, unless entering BACKUP or FAILSAFE state (ENx is pulled low in those states). 1 = ENx pin mapped to first time slot (first down). 15 = ENx pin mapped to last time slot (last down). |
Address: 0xF0, 0xF1
Description: Protection selection registers. In order to write-protect a register group, the host must set the relevant bit in both registers.
POR Value: 0x00
Access: Read/Write.
For security, these registers need to have POR value=0x00 and become read-only once set until power cycle.
Once set to 1, they cannot be cleared to 0 by the host; a power cycle (VDD=0) is required to write different registers configurations.
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BIT | NAME | DESCRIPTION |
---|---|---|
7 | RSVD | Reserved |
6 | WRK | 0 = Working registers are writable. 1 = Writes to working registers are ignored. |
5 | RSVD | RSVD |
4 | SEQP | 0 = Power Sequence registers are writable. 1 = Writes to Power Sequence registers are ignored. |
3 | SEQC | 0 = Sequence slot configuration registers are writable. 1 = Writes to Sequence slot configuration registers are ignored. |
2 | RSVD |
RSVD |
1 | RSVD | RSVD |
0 | CTL | 0 = Control registers are writable. 1 = Writes to control registers are ignored. |
Address: 0xF9
Description: I2C address.
POR Value: Loaded from NVM.
Access: Read-Only.
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BIT | NAME | DESCRIPTION |
---|---|---|
7 | RSVD | Reserved |
6:0 | ADDR_NVM[6:0] | I2C target device address. Set in NVM. |