SNVSCG1 Data sheet

SNVSCG1 july 2023 TPS38700S-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G

Thermal pad, mechanical data (Package|Pins)

RGE|24
- QFND723

Orderable Information

7.6 Timing Requirements

At 2.2 V ≤ VDD ≤ 5.5 V, NIRQ/NRST Voltage = 10 kΩ to VDD, NIRQ/NRST load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_A = 25°C, typical conditions at VDD = 3.3 V.

			MIN	MAX	UNIT
Common parameters
t_{D_ENx}	ENx toggle delay from start of time slot	From start of time slot		10	µs
t_{D_ENx,y}	Delay between 2 subsequent EN in same time slot			1	µs
t_{NRST_EN}	ENx delay from NRST in Emergency Shutdown	Sequence 2	200		ns
t_{D_NRST}	NRST assertion latency from falling edge of ACT pin below VIL or falling edge of VDD pin below VDD_min			25	µs
t_{D_NIRQ}	Fault detection to NIRQ assertion latency			25	µs
t_{No_BIST}	POR to ready without BIST	including OTP load with ECC		2.5	ms
I2C Timing Characteristics
f_SCL	Serial clock frequency ⁽¹⁾	Standard mode		100	kHz
f_SCL	Serial clock frequency ⁽¹⁾	Fast mode		400	kHz
f_SCL	Serial clock frequency ⁽¹⁾	Fast mode +		1	MHz
t_LOW	SCL low time ⁽¹⁾	Standard mode	4.7		µs
t_LOW	SCL low time ⁽¹⁾	Fast mode	1.3		µs
t_LOW	SCL low time ⁽¹⁾	Fast mode +	0.5		µs
t_HIGH	SCL high time ⁽¹⁾	Standard mode	4		µs
t_HIGH	SCL high time ⁽¹⁾	Fast Mode	1		µs
t_HIGH	SCL high time ⁽¹⁾	Fast mode +	0.26		µs
t_{SU_DAT}	Data setup time ⁽¹⁾	Standard mode	250		ns
t_{SU_DAT}	Data setup time ⁽¹⁾	Fast mode	100		ns
t_{SU_DAT}	Data setup time ⁽¹⁾	Fast mode +	50		ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Standard mode	10	3450	ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Fast mode	10	900	ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Fast mode +	10		ns
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Standard mode	4.7		µs
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Fast mode	0.6		µs
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Fast mode +	0.26		µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Standard mode	4		µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Fast mode	0.6		µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Fast mode +	0.26		µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Standard mode	4.7		µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Fast mode	1.3		µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Fast mode +	0.5		µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Standard mode	4		µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Fast mode	0.6		µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Fast mode +	0.26		µs
t_rDA	Rise time of SDA signal ⁽¹⁾	Standard mode		1000
t_rDA	Rise time of SDA signal ⁽¹⁾	Fast mode	20	300	ns
t_rDA	Rise time of SDA signal ⁽¹⁾	Fast mode +		120	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Standard mode		300	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Fast mode	1.4	300	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Fast mode +	6.5	120	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Standard mode		1000	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Fast mode	20	300	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Fast mode +		120	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Standard mode		300	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Fast mode	6.5	300	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Fast mode +	6.5	120	ns
t_SP	Pulse width of SCL and SDA spikes that are suppressed ⁽¹⁾	Standard mode, Fast mode and Fast mode +		50	ns

(1) Guaranteed by design