SBVS303B March   2017  – February 2018 TPS3890-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      VITN Accuracy vs Temperature
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 User-Configurable RESET Delay Time
      2. 8.3.2 Manual Reset (MR) Input
      3. 8.3.3 RESET Output
      4. 8.3.4 SENSE Input
        1. 8.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over the operating junction temperature range of –40°C to +125°C (TA = TJ), 1.5 V ≤ VDD ≤ 5.5 V, and MR = VDD (unless otherwise noted); typical values are at VDD = 5.5 V and TJ = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VDD Input supply voltage 1.5 5.5 V
VPOR Power-on-reset voltage VOL(max) = 0.2 V, IRESET = 15 µA 0.8 V
IDD Supply current (into VDD pin) VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 85°C		 2.09 3.72 µA
VDD = 3.3 V, IRESET = 0 mA,
–40°C < TJ < 105°C		 4.5
VDD= 3.3 V, IRESET = 0 mA 5.8
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 85°C		 2.29 4
VDD = 5.5 V, IRESET = 0 mA,
–40°C < TJ < 105°C		 5.2
VDD = 5.5 V, IRESET = 0 mA 6.5
VITN, VITP SENSE input threshold voltage accuracy –1% ±0.5% 1%
VHYST Hysteresis(1) 0.325% 0.575% 0.825%
ISENSE Input current VSENSE = 5 V 8 µA
VSENSE = 5 V, TPS389001-Q1, TPS389012-Q1 10 100 nA
ICT CT pin charge current 0.90 1.15 1.35 µA
VCT CT pin comparator threshold voltage 1.17 1.23 1.29 V
RCT CT pin pulldown resistance When RESET is deasserted 200 Ω
VIL Low-level input voltage (MR pin) 0.25 × VDD V
VIH High-level output voltage 0.7 x VDD V
VOL Low-level output voltage VDD ≥ 1.5 V, IRESET = 0.4 mA 0.25 V
VDD ≥ 2.7 V, IRESET = 2 mA 0.25
VDD ≥ 4.5 V, IRESET = 3 mA 0.3
ILKG(OD) Open-drain output leakage High impedance,
VSENSE = VRESET = 5.5 V		 250 nA
(1) VHYST = [(VITP – VITN) / VITN] × 100%.