SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 I2C

The TPS389006 device follows the I2C protocol (up to 1MHz) to manage communication with host devices such as a MCU or System on Chip (SoC). I2C is a two wire communication protocol implemented using two signals, clock (SCL) and data (SDA). The host device is the primary controller of communication. TPS389006 device responds over the data line during read or write operations as defined by I2C protocol. Both SCL and SDA signals are open drain topology and can be used in a wired-OR configuration with other devices to share the communication bus. Both SCL and SDA pins need an external pull up resistor to supply voltage (10kΩ recommended).

Figure 7-4 shows the timing relationship between SCL and SDA lines to transfer 1 byte of data. SCL line is always controlled by host. To transfer 1 byte data, host needs to send 9 clocks on SCL. 8 clocks for data and 1 clock for ACK or NACK. SDA line is controlled by either the host or TPS389006 device based on the read or write operation. Figure 7-4 and Figure 7-5 highlight the communication protocol flow and which device controls SDA line at various instances during active communication.

TPS389006-Q1 TPS389R0-Q1 SCL to SDA Timing for 1 Byte Data Transfer Figure 7-4 SCL to SDA Timing for 1 Byte Data Transfer
TPS389006-Q1 TPS389R0-Q1 I2C Write Protocol Figure 7-5 I2C Write Protocol
TPS389006-Q1 TPS389R0-Q1 I2C Read Protocol Figure 7-6 I2C Read Protocol

Before initiating communication over I2C protocol, host needs to confirm the I2C bus is available for communication. Monitor the SCL and SDA lines, if any line is pulled low, the I2C bus is occupied. Host needs to wait until the bus is available for communication. Once the bus is available for communication, the host can initiate read or write operation by issuing a START condition. Once the I2C communication is complete, release the bus by issuing STOP command. Figure 7-7 shows how to implement START and STOP condition.

TPS389006-Q1 TPS389R0-Q1 I2C START and STOP Condition Figure 7-7 I2C START and STOP Condition
Table 7-1 shows the different functionality available when programming with I2C.
Table 7-1 User Programmable I2C Functions
FUNCTIONS DESCRIPTION
Thresholds for OV/UV- fast loop Adjustable in 5mV steps from 0.2V to 1.475V and 20mV steps from 0.8V to 5.5V
Thresholds for drift -positive and negative Adjustable in 5mV steps from 0.2V to 1.475V and 20mV steps from 0.8V to 5.5V
Voltage Monitoring scaling 1 or 4
Glitch (debounce) immunity for OV/UV-fast loop 0.1 us to 102.4 us
Low pass filter cut off Frequency 250Hz to 4kHz
Enable sequence timeout 1ms to 4s
Sleep sequence timeout 1ms to 4s
SYNC pulse width 50us to 2600us
Expected ON/OFF Sequence on ACT Used for sequence logging
Expected ON/OFF Sequence on Sleep Used for sequence logging
Auto Mask OFF-ON-OFF via ACT Selectable for each MON channel
Auto Mask OFF-ON-OFF via SLEEP Selectable for each MON channel
Packet error checking for I2C Enabling or Disabling
Force NIRQ assertion Controlled by I2C register
Individual channel MON Enable or Disable
Interrupt disable functions BIST, PEC, TSD, CRC