SNVSBM4D
March 2022 – October 2024
TPS389006-Q1
,
TPS389R0-Q1
PRODMIX
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
I2C
7.3.2
Auto Mask (AMSK)
7.3.3
Packet Error Checking (PEC)
7.3.4
VDD
7.3.5
MON
7.3.6
NIRQ
7.3.7
ADC
7.3.8
Time Stamp
7.3.9
NRST
7.3.10
Register Protection
7.4
Device Functional Modes
7.4.1
Built-In Self Test and Configuration Load
7.4.1.1
Notes on BIST Execution
7.4.2
TPS389006/08-Q1,TPS389R0-Q1 Power ON
7.4.3
General Monitoring
7.4.3.1
IDLE Monitoring
7.4.3.2
ACTIVE Monitoring
7.4.3.3
Sequence Monitoring 1
7.4.3.3.1
ACT Transitions 0→1
7.4.3.3.2
SLEEP Transition 1→0
7.4.3.3.3
SLEEP Transition 0→1
7.4.3.4
Sequence Monitoring 2
7.4.3.4.1
ACT Transition 1→0
7.5
Register Maps
7.5.1
BANK0 Registers
7.5.2
BANK1 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Multichannel Sequencer and Monitor
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.4
Application Curves
8.3
Power Supply Recommendations
8.3.1
Power Supply Guidelines
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Nomenclature
9.2
Documentation Support
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTE|16
MPQF149D
Thermal pad, mechanical data (Package|Pins)
RTE|16
QFND630A
Orderable Information
snvsbm4d_oa
snvsbm4d_pm
9.7
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.