SNVSC50 Data sheet

SNVSC50 june 2023 TPS389006

PRODUCTION DATA

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Mechanical Data (Package|Pins)

RTE|16
- MPQF149D

Thermal pad, mechanical data (Package|Pins)

RTE|16
- QFND525B

Orderable Information

8.5.2 BANK1 Registers

Table 8-73 lists the memory-mapped registers for the BANK1 registers. All register offset addresses not listed in Table 8-73 should be considered as reserved locations and the register contents should not be modified.

Table 8-73 BANK1 Registers

Address	Acronym	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0x10	VMON_CTL	DIAG_EN_SCALE		SLP_PWR	RSVD	RESET_PROT	SYNC_RST	FORCE_SYNC	FORCE_NIRQ
0x11	VMON_MISC	RSVD				EN_TS_OW	EN_SEQ_OW	REQ_PEC	EN_PEC
0x12	TEST_CFG	RSVD				AT_SHDN	RESERVED	AT_POR
0x13	IEN_UVHF	RSVD		MON[N]
0x14	IEN_UVLF	RSVD		MON[N]
0x15	IEN_OVHF	RSVD		MON[N]
0x16	IEN_OVLF	RSVD		MON[N]
0x17	IEN_SEQ_ON	RSVD		MON[N]
0x18	IEN_SEQ_OFF	RSVD		MON[N]
0x19	IEN_SEQ_EXS	RSVD		MON[N]
0x1A	IEN_SEQ_ENS	RSVD		MON[N]
0x1B	IEN_CONTROL	RT_CRC Int				RSVD	TSD Int	SYNC Int	PEC Int
0x1C	IEN_TEST	ECC_SEC					RSVD	BIST_Complete_INT	BIST_Fail_INT
0x1E	MON_CH_EN	RSVD		MON[N]
0x1F	VRANGE_MULT	RSVD		MON[N]
0x20	UV_HF[1]	THRESHOLD[7:0]
0x21	OV_HF[1]	THRESHOLD[7:0]
0x22	UV_LF[1]	THRESHOLD[7:0]
0x23	OV_LF[1]	THRESHOLD[7:0]
0x24	FLT_HF[1]	OV_DEB[3:0]				UV_DEB[3:0]
0x25	FC_LF[1]	RSVD					THRESHOLD[2:0]
0x30	UV_HF[2]	THRESHOLD[7:0]
0x31	OV_HF[2]	THRESHOLD[7:0]
0x32	UV_LF[2]	THRESHOLD[7:0]
0x33	OV_LF[2]	THRESHOLD[7:0]
0x34	FLT_HF[2]	OV_DEB[3:0]				UV_DEB[3:0]
0x35	FC_LF[2]	RSVD					THRESHOLD[2:0]
0x40	UV_HF[3]	THRESHOLD[7:0]
0x41	OV_HF[3]	THRESHOLD[7:0]
0x42	UV_LF[3]	THRESHOLD[7:0]
0x43	OV_LF[3]	THRESHOLD[7:0]
0x44	FLT_HF[3]	OV_DEB[3:0]				UV_DEB[3:0]
0x45	FC_LF[3]	RSVD					THRESHOLD[2:0]
0x50	UV_HF[4]	THRESHOLD[7:0]
0x51	OV_HF[4]	THRESHOLD[7:0]
0x52	UV_LF[4]	THRESHOLD[7:0]
0x53	OV_LF[4]	THRESHOLD[7:0]
0x54	FLT_HF[4]	OV_DEB[3:0]				UV_DEB[3:0]
0x55	FC_LF[4]	RSVD					THRESHOLD[2:0]
0x60	UV_HF[5]	THRESHOLD[7:0]
0x61	OV_HF[5]	THRESHOLD[7:0]
0x62	UV_LF[5]	THRESHOLD[7:0]
0x63	OV_LF[5]	THRESHOLD[7:0]
0x64	FLT_HF[5]	OV_DEB[3:0]				UV_DEB[3:0]
0x65	FC_LF[5]	RSVD					THRESHOLD[2:0]
0x70	UV_HF[6]	THRESHOLD[7:0]
0x71	OV_HF[6]	THRESHOLD[7:0]
0x72	UV_LF[6]	THRESHOLD[7:0]
0x73	OV_LF[6]	THRESHOLD[7:0]
0x74	FLT_HF[6]	OV_DEB[3:0]				UV_DEB[3:0]
0x75	FC_LF[6]	RSVD					THRESHOLD[2:0]
0x9F	TI_CONTROL	ENTER_BIST	RSVD
0xA0	SEQ_REC_CTL	REC_START	SEQ[1:0]		TS_ACK	SEQ_ON_ACK	SEQ_OFF_ACK	SEQ_EXS_ACK	SEQ_ENS_ACK
0xA1	AMSK_ON	RSVD		MON[N]
0xA2	AMSK_OFF	RSVD		MON[N]
0xA3	AMSK_EXS	RSVD		MON[N]
0xA4	AMSK_ENS	RSVD		MON[N]
0xA5	SEQ_TOUT_MSB	MILLISEC[7:0]
0xA6	SEQ_TOUT_LSB	MILLISEC[7:0]
0xA7	SEQ_SYNC	PULSE_WIDTH[7:0]
0xA8	SEQ_UP_THLD	RSVD		MON[N]
0xA9	SEQ_DN_THLD	RSVD		MON[N]
0xB0	SEQ_ON_EXP[1]	ORDER[7:0]
0xB1	SEQ_ON_EXP[2]	ORDER[7:0]
0xB2	SEQ_ON_EXP[3]	ORDER[7:0]
0xB3	SEQ_ON_EXP[4]	ORDER[7:0]
0xB4	SEQ_ON_EXP[5]	ORDER[7:0]
0xB5	SEQ_ON_EXP[6]	ORDER[7:0]
0xC0	SEQ_OFF_EXP[1]	ORDER[7:0]
0xC1	SEQ_OFF_EXP[2]	ORDER[7:0]
0xC2	SEQ_OFF_EXP[3]	ORDER[7:0]
0xC3	SEQ_OFF_EXP[4]	ORDER[7:0]
0xC4	SEQ_OFF_EXP[5]	ORDER[7:0]
0xC5	SEQ_OFF_EXP[6]	ORDER[7:0]
0xD0	SEQ_EXS_EXP[1]	ORDER[7:0]
0xD1	SEQ_EXS_EXP[2]	ORDER[7:0]
0xD2	SEQ_EXS_EXP[3]	ORDER[7:0]
0xD3	SEQ_EXS_EXP[4]	ORDER[7:0]
0xD4	SEQ_EXS_EXP[5]	ORDER[7:0]
0xD5	SEQ_EXS_EXP[6]	ORDER[7:0]
0xE0	SEQ_ENS_EXP[1]	ORDER[7:0]
0xE1	SEQ_ENS_EXP[2]	ORDER[7:0]
0xE2	SEQ_ENS_EXP[3]	ORDER[7:0]
0xE3	SEQ_ENS_EXP[4]	ORDER[7:0]
0xE4	SEQ_ENS_EXP[5]	ORDER[7:0]
0xE5	SEQ_ENS_EXP[6]	ORDER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 8-74 shows the codes that are used for access types in this section.

Table 8-74 BANK1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.5.2.1 VMON_CTL Register (Address = 0x10) [Default = X]

VMON_CTL is shown in Table 8-75.

Return to the Summary Table.

Voltage Monitor device control register.

Table 8-75 VMON_CTL Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	DIAG_EN_SCALE	R/W	0b	Diag EN Scale 00 = No force on GAINSEL of SVS COMPs 01 = Forced to 1x 10 = Forced to 2x 11 = Forced to 4x
5	SLP_PWR	R/W	0b	Sleep Power Bit 0 = Sleep low power mode 1 = Sleep high power mode
4	RSVD	R/W	X	RSVD
3	RESET_PROT	R/W	0b	Reset 0 = Always reads 0 1 = Full device Reset
2	SYNC_RST	R/W	0b	SYNC counter reset (SEQ_ORD_STAT.SYNC_COUNT). 0 = Always reads 0 1 = Reset SYNC counter
1	FORCE_SYNC	R/W	0b	Force SYNC assertion 0 =SYNC pin is de-asserted and controlled by the sequence monitoring logic. 1 =SYNC pin is asserted (forced low)
0	FORCE_NIRQ	R/W	0b	Force NIRQ assertion 0 = NIRQ pin is de-asserted and controlled by interrupt registers faults 1 = NIRQ pin is asserted (forced low)

8.5.2.2 VMON_MISC Register (Address = 0x11) [Default = X]

VMON_MISC is shown in Table 8-76.

Return to the Summary Table.

Miscellaneous voltage monitoring configurations.

Table 8-76 VMON_MISC Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	RSVD	R/W	X	RSVD
3	EN_TS_OW	R/W	1b	Allow Timestamp recording overwrite 0 = Disabled. If sequence timestamp data is available in the SEQ_TIME_xSB[N] registers and the SEQ_REC_STAT.TS_RDY bit is set (data not read yet), a new sequence will not overwrite the existing data. 1 = Enabled (default). Sequence timestamp data is overwritten with a new sequence, irrelevant of the SEQ_REC_STAT.TS_RDY bit.
2	EN_SEQ_OW	R/W	1b	Allow Sequence Order recording overwrite 0 = Disabled. If sequence order data is available in the SEQ_ON_LOG[N], SEQ_OFF_LOG[N], SEQ_EXS_LOG[N], or SEQ_ENS_LOG[N] registers, and the respective SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit is set (data not read yet), a new sequence will not overwrite the existing data. 1 = Enabled (default). Sequence order data is overwritten with a new sequence, regradless of the SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit.
1	REQ_PEC	R/W	0b	Require PEC byte (valid only if EN_PEC is 1): 0 = missing PEC byte is treated as good PEC 1 = missing PEC byte is treated as bad PEC, triggering a fault
0	EN_PEC	R/W	0b	PEC: 0 = PEC disabled (default) 1 = PEC enabled

8.5.2.3 TEST_CFG Register (Address = 0x12) [Default = X]

TEST_CFG is shown in Table 8-77.

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Built-In Self Test BIST execution configuration.

Table 8-77 TEST_CFG Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	RSVD	R/W	X	RSVD
3	AT_SHDN	R/W	X	Run BIST when exiting ACTIVE state due to ACT transitioning 1 to 0. Device ready after tCFG_WB. This bit cannot be set in OTP/NVM. Always defaults to 0 when loading configuration from OTP/NVM.
2	RESERVED	R	X
1:0	AT_POR	R/W	X	Run BIST at POR. Device ready after tCFG_WB. 00b = Valid OTP configuration, skip BIST at POR 01b = Corrupt OTP configuration, run BIST at POR 10b = Corrupt OTP configuration, run BIST at POR 11b = Valid OTP configuration, run BIST at POR

8.5.2.4 IEN_UVHF Register (Address = 0x13) [Default = X]

IEN_UVHF is shown in Table 8-78.

Return to the Summary Table.

High Frequency channel Undervoltage Interrupt Enable register.

Table 8-78 IEN_UVHF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Undervoltage High Frequency fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.5 IEN_UVLF Register (Address = 0x14) [Default = X]

IEN_UVLF is shown in Table 8-79.

Return to the Summary Table.

Low Frequency channel Undervoltage Interrupt Enable register.

Table 8-79 IEN_UVLF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Undervoltage Low Frequency fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.6 IEN_OVHF Register (Address = 0x15) [Default = X]

IEN_OVHF is shown in Table 8-80.

Return to the Summary Table.

High Frequency channel Overvoltage Interrupt Enable register.

Table 8-80 IEN_OVHF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Overvoltage High Frequency fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.7 IEN_OVLF Register (Address = 0x16) [Default = X]

IEN_OVLF is shown in Table 8-81.

Return to the Summary Table.

Low Frequency channel Overvoltage Interrupt Enable register.

Table 8-81 IEN_OVLF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Overvoltage Low Frequency fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.8 IEN_SEQ_ON Register (Address = 0x17) [Default = X]

IEN_SEQ_ON is shown in Table 8-82.

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Power ON Sequence ACT transition 0 to 1 Interrupt Enable register.

Table 8-82 IEN_SEQ_ON Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Power ON Sequence Fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.9 IEN_SEQ_OFF Register (Address = 0x18) [Default = X]

IEN_SEQ_OFF is shown in Table 8-83.

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Power OFF Sequence ACT transition 1 to 0 Interrupt Enable register.

Table 8-83 IEN_SEQ_OFF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Power OFF Sequence Fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.10 IEN_SEQ_EXS Register (Address = 0x19) [Default = X]

IEN_SEQ_EXS is shown in Table 8-84.

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Exit Sleep Sequence SLEEP transition 0 to 1 Interrupt Enable register.

Table 8-84 IEN_SEQ_EXS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Exit Sleep Sequence Fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.11 IEN_SEQ_ENS Register (Address = 0x1A) [Default = X]

IEN_SEQ_ENS is shown in Table 8-85.

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Entry Sleep Sequence SLEEP transition 1 to 0 Interrupt Enable register.

Table 8-85 IEN_SEQ_ENS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Entry Sleep Sequence Fault Interrupt Enable for VIN channel N (1 through 6). 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.12 IEN_CONTROL Register (Address = 0x1B) [Default = X]

IEN_CONTROL is shown in Table 8-86.

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Control and Communication Fault Interrupt Enable register.

Table 8-86 IEN_CONTROL Register Field Descriptions

Bit	Field	Type	Default	Description
7:5	RSVD	R/W	X	RSVD
4	RT_CRC Int	R/W	0b	Runtime register Cyclic Redundancy Check (CRC) fault interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled
3	RSVD	R/W	X	RSVD
2	TSD Int	R/W	0b	Thermal Shutdown fault interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled
1	SYNC Int	R/W	0b	SYNC pin fault (short to supply or ground detected on SYNC pin) interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled
0	PEC Int	R/W	0b	PEC fault (mismatch) interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled

8.5.2.13 IEN_TEST Register (Address = 0x1C) [Default = X]

IEN_TEST is shown in Table 8-87.

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Internal Test and Configuration Load Fault Interrupt Enable register.

Table 8-87 IEN_TEST Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	RSVD	R/W	X	RSVD
3	ECC_SEC	R/W	0b	ECC single-error correction fault (on OTP load) interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled
2	RSVD	R/W	X	RSVD
1	BIST_Complete_INT	R/W	0b	Built-In Self-Test complete interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled
0	BIST_Fail_INT	R/W	0b	Built-In Self-Test fault interrupt enable: 0 = Interrupt disabled 1 = Interrupt enabled Although expected to be always enabled, it is desirable to have the option to disable it.

8.5.2.14 MON_CH_EN Register (Address = 0x1E) [Default = X]

MON_CH_EN is shown in Table 8-88.

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Channel 1-6 Voltage Monitoring Enable register.

Table 8-88 MON_CH_EN Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Voltage Monitoring Enable for VIN channel N (1 through 6). 0 = Channel Monitor disabled 1 = Channel Monitor enabled

8.5.2.15 VRANGE_MULT Register (Address = 0x1F) [Default = X]

VRANGE_MULT is shown in Table 8-89.

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Channel 1-6 Voltage Monitoring Range/Scaling register.

Table 8-89 VRANGE_MULT Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	0b	Voltage Monitoring Range/Scaling for VIN channel N (1 through 6). 0 = 1x scaling (0.2 V to 1.475 V with 5 mV steps) 1 = 4x scaling (0.8 V to 5.9 V with 20 mV steps)

8.5.2.16 UV_HF[1] Register (Address = 0x20) [Default = 0x00]

UV_HF[1] is shown in Table 8-90.

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Channel 1 High Frequency channel Undervoltage threshold.

Table 8-90 UV_HF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.17 OV_HF[1] Register (Address = 0x21) [Default = 0xFF]

OV_HF[1] is shown in Table 8-91.

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Channel 1 High Frequency channel Overvoltage threshold.

Table 8-91 OV_HF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.18 UV_LF[1] Register (Address = 0x22) [Default = 0x00]

UV_LF[1] is shown in Table 8-92.

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Channel 1 Low Frequency channel Undervoltage threshold.

Table 8-92 UV_LF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.19 OV_LF[1] Register (Address = 0x23) [Default = 0xFF]

OV_LF[1] is shown in Table 8-93.

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Channel 1 Low Frequency channel Overvoltage threshold.

Table 8-93 OV_LF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.20 FLT_HF[1] Register (Address = 0x24) [Default = 0x00]

FLT_HF[1] is shown in Table 8-94.

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Channel 1 debounce filter for High Frequency Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-94 FLT_HF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.21 FC_LF[1] Register (Address = 0x25) [Default = X]

FC_LF[1] is shown in Table 8-95.

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Channel 1 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-95 FC_LF[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	Low frequency cutoff. 000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.22 UV_HF[2] Register (Address = 0x30) [Default = 0x00]

UV_HF[2] is shown in Table 8-96.

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Channel 2 High Frequency channel Undervoltage threshold.

Table 8-96 UV_HF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.23 OV_HF[2] Register (Address = 0x31) [Default = 0xFF]

OV_HF[2] is shown in Table 8-97.

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Channel 2 High Frequency channel Overvoltage threshold.

Table 8-97 OV_HF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.24 UV_LF[2] Register (Address = 0x32) [Default = 0x00]

UV_LF[2] is shown in Table 8-98.

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Channel 2 Low Frequency channel Undervoltage threshold.

Table 8-98 UV_LF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.25 OV_LF[2] Register (Address = 0x33) [Default = 0xFF]

OV_LF[2] is shown in Table 8-99.

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Channel 2 Low Frequency channel Overvoltage threshold.

Table 8-99 OV_LF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.26 FLT_HF[2] Register (Address = 0x34) [Default = 0x00]

FLT_HF[2] is shown in Table 8-100.

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Channel 2 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-100 FLT_HF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.27 FC_LF[2] Register (Address = 0x35) [Default = X]

FC_LF[2] is shown in Table 8-101.

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Channel 2 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-101 FC_LF[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.28 UV_HF[3] Register (Address = 0x40) [Default = 0x00]

UV_HF[3] is shown in Table 8-102.

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Channel 3 High Frequency channel Undervoltage threshold.

Table 8-102 UV_HF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.29 OV_HF[3] Register (Address = 0x41) [Default = 0xFF]

OV_HF[3] is shown in Table 8-103.

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Channel 3 High Frequency channel Overvoltage threshold.

Table 8-103 OV_HF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.30 UV_LF[3] Register (Address = 0x42) [Default = 0x00]

UV_LF[3] is shown in Table 8-104.

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Channel 3 Low Frequency channel Undervoltage threshold.

Table 8-104 UV_LF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.31 OV_LF[3] Register (Address = 0x43) [Default = 0xFF]

OV_LF[3] is shown in Table 8-105.

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Channel 3 Low Frequency channel Overvoltage threshold.

Table 8-105 OV_LF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.32 FLT_HF[3] Register (Address = 0x44) [Default = 0x00]

FLT_HF[3] is shown in Table 8-106.

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Channel 3 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-106 FLT_HF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.33 FC_LF[3] Register (Address = 0x45) [Default = X]

FC_LF[3] is shown in Table 8-107.

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Channel 3 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-107 FC_LF[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.34 UV_HF[4] Register (Address = 0x50) [Default = 0x00]

UV_HF[4] is shown in Table 8-108.

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Channel 4 High Frequency channel Undervoltage threshold.

Table 8-108 UV_HF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.35 OV_HF[4] Register (Address = 0x51) [Default = 0xFF]

OV_HF[4] is shown in Table 8-109.

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Channel 4 High Frequency channel Overvoltage threshold.

Table 8-109 OV_HF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.36 UV_LF[4] Register (Address = 0x52) [Default = 0x00]

UV_LF[4] is shown in Table 8-110.

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Channel 4 Low Frequency channel Undervoltage threshold.

Table 8-110 UV_LF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.37 OV_LF[4] Register (Address = 0x53) [Default = 0xFF]

OV_LF[4] is shown in Table 8-111.

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Channel 4 Low Frequency channel Overvoltage threshold.

Table 8-111 OV_LF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.38 FLT_HF[4] Register (Address = 0x54) [Default = 0x00]

FLT_HF[4] is shown in Table 8-112.

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Channel 4 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-112 FLT_HF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.39 FC_LF[4] Register (Address = 0x55) [Default = X]

FC_LF[4] is shown in Table 8-113.

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Channel 4 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-113 FC_LF[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.40 UV_HF[5] Register (Address = 0x60) [Default = 0x00]

UV_HF[5] is shown in Table 8-114.

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Channel 5 High Frequency channel Undervoltage threshold.

Table 8-114 UV_HF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.41 OV_HF[5] Register (Address = 0x61) [Default = 0xFF]

OV_HF[5] is shown in Table 8-115.

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Channel 5 High Frequency channel Overvoltage threshold.

Table 8-115 OV_HF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.42 UV_LF[5] Register (Address = 0x62) [Default = 0x00]

UV_LF[5] is shown in Table 8-116.

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Channel 5 Low Frequency channel Undervoltage threshold.

Table 8-116 UV_LF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.43 OV_LF[5] Register (Address = 0x63) [Default = 0xFF]

OV_LF[5] is shown in Table 8-117.

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Channel 5 Low Frequency channel Overvoltage threshold.

Table 8-117 OV_LF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.44 FLT_HF[5] Register (Address = 0x64) [Default = 0x00]

FLT_HF[5] is shown in Table 8-118.

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Channel 5 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-118 FLT_HF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.45 FC_LF[5] Register (Address = 0x65) [Default = X]

FC_LF[5] is shown in Table 8-119.

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Channel 5 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-119 FC_LF[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.46 UV_HF[6] Register (Address = 0x70) [Default = 0x00]

UV_HF[6] is shown in Table 8-120.

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Channel 6 High Frequency channel Undervoltage threshold.

Table 8-120 UV_HF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.47 OV_HF[6] Register (Address = 0x71) [Default = 0xFF]

OV_HF[6] is shown in Table 8-121.

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Channel 6 High Frequency channel Overvoltage threshold.

Table 8-121 OV_HF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for High Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.48 UV_LF[6] Register (Address = 0x72) [Default = 0x00]

UV_LF[6] is shown in Table 8-122.

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Channel 6 Low Frequency channel Undervoltage threshold.

Table 8-122 UV_LF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	0b	Undervoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.49 OV_LF[6] Register (Address = 0x73) [Default = 0xFF]

OV_LF[6] is shown in Table 8-123.

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Channel 6 Low Frequency channel Overvoltage threshold.

Table 8-123 OV_LF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	THRESHOLD[7:0]	R/W	11111111b	Overvoltage threshold for Low Frequency component of monitored channel. The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT. With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV. With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.50 FLT_HF[6] Register (Address = 0x74) [Default = 0x00]

FLT_HF[6] is shown in Table 8-124.

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Channel 6 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-124 FLT_HF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:4	OV_DEB[3:0]	R/W	0b	Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0	UV_DEB[3:0]	R/W	0b	Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path. 0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.51 FC_LF[6] Register (Address = 0x75) [Default = X]

FC_LF[6] is shown in Table 8-125.

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Channel 6 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-125 FC_LF[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:3	RSVD	R/W	X	RSVD
2:0	THRESHOLD[2:0]	R/W	100b	000b = Invalid 001b = Invalid 010b = 250 Hz 011b = 500 Hz 100b = 1 kHz (default) 101b = 2 kHz 110b = 4 kHz 111b = Invalid

8.5.2.52 TI_CONTROL Register (Address = 0x9F) [Default = X]

TI_CONTROL is shown in Table 8-126.

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Manual BIST entry register.

Table 8-126 TI_CONTROL Register Field Descriptions

Bit	Field	Type	Default	Description
7	ENTER_BIST	R/W	X	Enter BIST: 0 = Default 1 = Enter BIST
6:0	RSVD	R/W	X	RSVD

8.5.2.53 SEQ_REC_CTL Register (Address = 0xA0) [Default = 0x00]

SEQ_REC_CTL is shown in Table 8-127.

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Sequence control register.

Table 8-127 SEQ_REC_CTL Register Field Descriptions

Bit	Field	Type	Default	Description
7	REC_START	R/W	0b	Software start sequence logging (recording): 0 = Always read 0 1 = Initiate power sequence (selected by SEQ[1:0]) recording.
6:5	SEQ[1:0]	R/W	0b	Sequence to record (and compare for faults to corresponding expected sequence order registers): 00b = Power ON (same as ACT 0 to 1) 01b = Power OFF (ACT 1 to 0) 10b = Sleep Exit (SLEEP 0 to 1) 11b = Sleep Entry (SLEEP 1 to 0)
4	TS_ACK	R/W	0b	Timestamp data OK to overwrite. Valid and used only if VMON_MISC.EN_TS_OW=0. 00b = Always read 0 01b = Acknowledge Timestamp data and OK to overwrite. SEQ_REC_STAT.TS_RDY and SEQ_OW_STAT.TS_OW are cleared.
3	SEQ_ON_ACK	R/W	0b	Power ON sequence data OK to overwrite. Valid and used only if VMON_MISC.EN_SEQ_OW=0. 00b = Always read 0 01b = Acknowledge Power ON sequence data and OK to overwrite. SEQ_REC_STAT.SEQ_ON_RDY and SEQ_OW_STAT.SEQ_ON_OW are cleared.
2	SEQ_OFF_ACK	R/W	0b	Power OFF sequence data OK to overwrite. Valid and used only if VMON_MISC.EN_SEQ_OW=0. 00b = Always read 0 01b = Acknowledge Power OFF sequence data and OK to overwrite. SEQ_REC_STAT.SEQ_OFF_RDY and SEQ_OW_STAT.SEQ_OFF_OW are cleared.
1	SEQ_EXS_ACK	R/W	0b	Sleep Exit sequence data OK to overwrite. Valid and used only if VMON_MISC.EN_SEQ_OW=0. 00b = Always read 0 01b = Acknowledge Sleep Exit sequence data and OK to overwrite. SEQ_REC_STAT.SEQ_EXS_RDY and SEQ_OW_STAT.SEQ_EXS_OW are cleared.
0	SEQ_ENS_ACK	R/W	0b	Sleep Entry sequence data OK to overwrite. Valid and used only if VMON_MISC.EN_SEQ_OW=0. 00b = Always read 0 01b = Acknowledge Sleep Entry sequence data and OK to overwrite. SEQ_REC_STAT.SEQ_ENS_RDY and SEQ_OW_STAT.SEQ_ENS_OW are cleared.

8.5.2.54 AMSK_ON Register (Address = 0xA1) [Default = X]

AMSK_ON is shown in Table 8-128.

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Auto-mask ON register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 0 to 1 transitions.

Table 8-128 AMSK_ON Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	111111b	Auto-mask on ACT 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6). 00b = Channel interrupts not auto-masked 01b = Channel interrupts auto-masked

8.5.2.55 AMSK_OFF Register (Address = 0xA2) [Default = X]

AMSK_OFF is shown in Table 8-129.

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Auto-mask OFF register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 1 to 0 transitions.

Table 8-129 AMSK_OFF Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	111111b	Auto-mask on ACT 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6). 00b = Channel interrupts not auto-masked 01b = Channel interrupts auto-masked

8.5.2.56 AMSK_EXS Register (Address = 0xA3) [Default = X]

AMSK_EXS is shown in Table 8-130.

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Auto-mask EXIT register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 0 to 1 transitions.

Table 8-130 AMSK_EXS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	111111b	Auto-mask on SLEEP 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6). 00b = Channel interrupts not auto-masked 01b = Channel interrupts auto-masked

8.5.2.57 AMSK_ENS Register (Address = 0xA4) [Default = X]

AMSK_ENS is shown in Table 8-131.

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Auto-mask ENTRY register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 1 to 0 transitions.

Table 8-131 AMSK_ENS Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	X	RSVD
5:0	MON[N]	R/W	111111b	Auto-mask on SLEEP 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6). 00b = Channel interrupts not auto-masked 01b = Channel interrupts auto-masked

8.5.2.58 SEQ_TOUT_MSB Register (Address = 0xA5) [Default = 0x00]

SEQ_TOUT_MSB is shown in Table 8-132.

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Sequence timeout most significant bits register.

Table 8-132 SEQ_TOUT_MSB Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	MILLISEC[7:0]	R/W	0b	ACT and SLEEP transition sequence timeout. After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active. 0x 0000 = 1 ms 0x 0001 = 2 ms While the max value is not specified, it is desirable to be able to set this timeout up to 4 s, and at least 256 ms (using only the lower byte at address 0xA6).

8.5.2.59 SEQ_TOUT_LSB Register (Address = 0xA6) [Default = 0x00]

SEQ_TOUT_LSB is shown in Table 8-133.

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Sequence timeout least significant bits register.

Table 8-133 SEQ_TOUT_LSB Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	MILLISEC[7:0]	R/W	0b	ACT and SLEEP transition sequence timeout. After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active. 0x 0000 = 1 ms 0x 0001 = 2 ms While the max value is not specified, it is desirable to be able to set this timeout up to 4 s, and at least 256 ms (using only the lower byte at address 0xA6).

8.5.2.60 SEQ_SYNC Register (Address = 0xA7) [Default = 0x00]

SEQ_SYNC is shown in Table 8-134.

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Sequence SYNC pulse duration from 50 us to 2600 us.

Table 8-134 SEQ_SYNC Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	PULSE_WIDTH[7:0]	R/W	0b	Pulse width for SYNC synchronization pulse. 00000000b = 50µs 00000001b = 60µs 00000010b = 70µs ... 11111101b = 2580µs 11111110b = 2590µs 11111111b = 2600µs

8.5.2.61 SEQ_UP_THLD Register (Address = 0xA8) [Default = 0xDF]

SEQ_UP_THLD is shown in Table 8-135.

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Threshold selection register for up sequence tagging ACT and SLEEP transition 0 to 1 transitions.

Table 8-135 SEQ_UP_THLD Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	11b	RSVD
5:0	MON[N]	R/W	11111b	OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power ON and Exit Sleep sequence tagging: 00b = Use OFF threshold (200 mV) 01b = Use UV threshold (UV_LF[N] register) 0b = OFF 1b = UVLF

8.5.2.62 SEQ_DN_THLD Register (Address = 0xA9) [Default = 0x00]

SEQ_DN_THLD is shown in Table 8-136.

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Threshold selection register for down sequence tagging ACT and SLEEP transition 1 to 0 transitions.

Table 8-136 SEQ_DN_THLD Register Field Descriptions

Bit	Field	Type	Default	Description
7:6	RSVD	R/W	0b	RSVD
5:0	MON[N]	R/W	0b	OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power OFF and Enter Sleep sequence tagging: 00b = Use OFF threshold (200 mV) 01b = Use UV threshold (UV_LF[N] register) 0b = OFF 1b = UVLF

8.5.2.63 SEQ_ON_EXP[1] Register (Address = 0xB0) [Default = 0x00]

SEQ_ON_EXP[1] is shown in Table 8-137.

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Channel 1 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 1.

Table 8-137 SEQ_ON_EXP[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 1. This sequence order value is compared with the SEQ_ON_LOG[1] register assigned to the channel during the sequence triggered by ACT.

8.5.2.64 SEQ_ON_EXP[2] Register (Address = 0xB1) [Default = 0x00]

SEQ_ON_EXP[2] is shown in Table 8-138.

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Channel 2 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 2.

Table 8-138 SEQ_ON_EXP[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 2. This sequence order value is compared with the SEQ_ON_LOG[2] register assigned to the channel during the sequence triggered by ACT.

8.5.2.65 SEQ_ON_EXP[3] Register (Address = 0xB2) [Default = 0x00]

SEQ_ON_EXP[3] is shown in Table 8-139.

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Channel 3 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 3

Table 8-139 SEQ_ON_EXP[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 3. This sequence order value is compared with the SEQ_ON_LOG[3] register assigned to the channel during the sequence triggered by ACT.

8.5.2.66 SEQ_ON_EXP[4] Register (Address = 0xB3) [Default = 0x00]

SEQ_ON_EXP[4] is shown in Table 8-140.

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Channel 4 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 4.

Table 8-140 SEQ_ON_EXP[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 4. This sequence order value is compared with the SEQ_ON_LOG[4] register assigned to the channel during the sequence triggered by ACT.

8.5.2.67 SEQ_ON_EXP[5] Register (Address = 0xB4) [Default = 0x00]

SEQ_ON_EXP[5] is shown in Table 8-141.

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Channel 5 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 5.

Table 8-141 SEQ_ON_EXP[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 5. This sequence order value is compared with the SEQ_ON_LOG[5] register assigned to the channel during the sequence triggered by ACT.

8.5.2.68 SEQ_ON_EXP[6] Register (Address = 0xB5) [Default = 0x00]

SEQ_ON_EXP[6] is shown in Table 8-142.

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Channel 6 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 6.

Table 8-142 SEQ_ON_EXP[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power ON sequence order value for channel 6. This sequence order value is compared with the SEQ_ON_LOG[6] register assigned to the channel during the sequence triggered by ACT.

8.5.2.69 SEQ_OFF_EXP[1] Register (Address = 0xC0) [Default = 0x00]

SEQ_OFF_EXP[1] is shown in Table 8-143.

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Channel 1 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 1.

Table 8-143 SEQ_OFF_EXP[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 1. This sequence order value is compared with the SEQ_OFF_LOG[1] register assigned to the channel during the sequence triggered by ACT

8.5.2.70 SEQ_OFF_EXP[2] Register (Address = 0xC1) [Default = 0x00]

SEQ_OFF_EXP[2] is shown in Table 8-144.

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Channel 2 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 2.

Table 8-144 SEQ_OFF_EXP[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 2. This sequence order value is compared with the SEQ_OFF_LOG[2] register assigned to the channel during the sequence triggered by ACT

8.5.2.71 SEQ_OFF_EXP[3] Register (Address = 0xC2) [Default = 0x00]

SEQ_OFF_EXP[3] is shown in Table 8-145.

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Channel 3 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 3.

Table 8-145 SEQ_OFF_EXP[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 3. This sequence order value is compared with the SEQ_OFF_LOG[3] register assigned to the channel during the sequence triggered by ACT

8.5.2.72 SEQ_OFF_EXP[4] Register (Address = 0xC3) [Default = 0x00]

SEQ_OFF_EXP[4] is shown in Table 8-146.

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Channel 4 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 4.

Table 8-146 SEQ_OFF_EXP[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 4. This sequence order value is compared with the SEQ_OFF_LOG[4] register assigned to the channel during the sequence triggered by ACT

8.5.2.73 SEQ_OFF_EXP[5] Register (Address = 0xC4) [Default = 0x00]

SEQ_OFF_EXP[5] is shown in Table 8-147.

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Channel 5 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 5.

Table 8-147 SEQ_OFF_EXP[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 5. This sequence order value is compared with the SEQ_OFF_LOG[5] register assigned to the channel during the sequence triggered by ACT

8.5.2.74 SEQ_OFF_EXP[6] Register (Address = 0xC5) [Default = 0x00]

SEQ_OFF_EXP[6] is shown in Table 8-148.

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Channel 6 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 6.

Table 8-148 SEQ_OFF_EXP[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Power OFF sequence order value for channel 6. This sequence order value is compared with the SEQ_OFF_LOG[6] register assigned to the channel during the sequence triggered by ACT

8.5.2.75 SEQ_EXS_EXP[1] Register (Address = 0xD0) [Default = 0x00]

SEQ_EXS_EXP[1] is shown in Table 8-149.

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Channel 1 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 1

Table 8-149 SEQ_EXS_EXP[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 1. This sequence order value is compared with the SEQ_EXS_LOG[1] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.76 SEQ_EXS_EXP[2] Register (Address = 0xD1) [Default = 0x00]

SEQ_EXS_EXP[2] is shown in Table 8-150.

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Channel 2 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 2

Table 8-150 SEQ_EXS_EXP[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 2. This sequence order value is compared with the SEQ_EXS_LOG[2] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.77 SEQ_EXS_EXP[3] Register (Address = 0xD2) [Default = 0x00]

SEQ_EXS_EXP[3] is shown in Table 8-151.

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Channel 3 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 3

Table 8-151 SEQ_EXS_EXP[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 3. This sequence order value is compared with the SEQ_EXS_LOG[3] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.78 SEQ_EXS_EXP[4] Register (Address = 0xD3) [Default = 0x00]

SEQ_EXS_EXP[4] is shown in Table 8-152.

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Channel 4 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 4

Table 8-152 SEQ_EXS_EXP[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 4. This sequence order value is compared with the SEQ_EXS_LOG[4] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.79 SEQ_EXS_EXP[5] Register (Address = 0xD4) [Default = 0x00]

SEQ_EXS_EXP[5] is shown in Table 8-153.

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Channel 5 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 5

Table 8-153 SEQ_EXS_EXP[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 5. This sequence order value is compared with the SEQ_EXS_LOG[5] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.80 SEQ_EXS_EXP[6] Register (Address = 0xD5) [Default = 0x00]

SEQ_EXS_EXP[6] is shown in Table 8-154.

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Channel 6 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 6

Table 8-154 SEQ_EXS_EXP[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Exit sequence order value for channel 6. This sequence order value is compared with the SEQ_EXS_LOG[6] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.81 SEQ_ENS_EXP[1] Register (Address = 0xE0) [Default = 0x00]

SEQ_ENS_EXP[1] is shown in Table 8-155.

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Channel 1 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 1

Table 8-155 SEQ_ENS_EXP[1] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 1. This sequence order value is compared with the SEQ_ENS_LOG[1] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.82 SEQ_ENS_EXP[2] Register (Address = 0xE1) [Default = 0x00]

SEQ_ENS_EXP[2] is shown in Table 8-156.

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Channel 2 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 2

Table 8-156 SEQ_ENS_EXP[2] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 2. This sequence order value is compared with the SEQ_ENS_LOG[2] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.83 SEQ_ENS_EXP[3] Register (Address = 0xE2) [Default = 0x00]

SEQ_ENS_EXP[3] is shown in Table 8-157.

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Channel 3 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 3

Table 8-157 SEQ_ENS_EXP[3] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 3. This sequence order value is compared with the SEQ_ENS_LOG[3] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.84 SEQ_ENS_EXP[4] Register (Address = 0xE3) [Default = 0x00]

SEQ_ENS_EXP[4] is shown in Table 8-158.

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Channel 4 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 4

Table 8-158 SEQ_ENS_EXP[4] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 4. This sequence order value is compared with the SEQ_ENS_LOG[4] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.85 SEQ_ENS_EXP[5] Register (Address = 0xE4) [Default = 0x00]

SEQ_ENS_EXP[5] is shown in Table 8-159.

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Channel 5 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 5

Table 8-159 SEQ_ENS_EXP[5] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 5. This sequence order value is compared with the SEQ_ENS_LOG[5] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.86 SEQ_ENS_EXP[6] Register (Address = 0xE5) [Default = 0x00]

SEQ_ENS_EXP[6] is shown in Table 8-160.

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Channel 6 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 6

Table 8-160 SEQ_ENS_EXP[6] Register Field Descriptions

Bit	Field	Type	Default	Description
7:0	ORDER[7:0]	R/W	0b	Expected Sleep Entry sequence order value for channel 6. This sequence order value is compared with the SEQ_ENS_LOG[6] register assigned to the channel during the sequence triggered by SLEEP.