SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

BANK1 Registers

Table 8-73 lists the memory-mapped registers for the BANK1 registers. All register offset addresses not listed in Table 8-73 should be considered as reserved locations and the register contents should not be modified.

Table 8-73 BANK1 Registers
AddressAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x10VMON_CTLDIAG_EN_SCALESLP_PWRRSVDRESET_PROTSYNC_RSTFORCE_SYNCFORCE_NIRQ
0x11VMON_MISCRSVDEN_TS_OWEN_SEQ_OWREQ_PECEN_PEC
0x12TEST_CFGRSVDAT_SHDNRESERVEDAT_POR
0x13IEN_UVHFRSVDMON[N]
0x14IEN_UVLFRSVDMON[N]
0x15IEN_OVHFRSVDMON[N]
0x16IEN_OVLFRSVDMON[N]
0x17IEN_SEQ_ONRSVDMON[N]
0x18IEN_SEQ_OFFRSVDMON[N]
0x19IEN_SEQ_EXSRSVDMON[N]
0x1AIEN_SEQ_ENSRSVDMON[N]
0x1BIEN_CONTROLRT_CRC IntRSVDTSD IntSYNC IntPEC Int
0x1CIEN_TESTECC_SECRSVDBIST_Complete_INTBIST_Fail_INT
0x1EMON_CH_ENRSVDMON[N]
0x1FVRANGE_MULTRSVDMON[N]
0x20UV_HF[1]THRESHOLD[7:0]
0x21OV_HF[1]THRESHOLD[7:0]
0x22UV_LF[1]THRESHOLD[7:0]
0x23OV_LF[1]THRESHOLD[7:0]
0x24FLT_HF[1]OV_DEB[3:0]UV_DEB[3:0]
0x25FC_LF[1]RSVDTHRESHOLD[2:0]
0x30UV_HF[2]THRESHOLD[7:0]
0x31OV_HF[2]THRESHOLD[7:0]
0x32UV_LF[2]THRESHOLD[7:0]
0x33OV_LF[2]THRESHOLD[7:0]
0x34FLT_HF[2]OV_DEB[3:0]UV_DEB[3:0]
0x35FC_LF[2]RSVDTHRESHOLD[2:0]
0x40UV_HF[3]THRESHOLD[7:0]
0x41OV_HF[3]THRESHOLD[7:0]
0x42UV_LF[3]THRESHOLD[7:0]
0x43OV_LF[3]THRESHOLD[7:0]
0x44FLT_HF[3]OV_DEB[3:0]UV_DEB[3:0]
0x45FC_LF[3]RSVDTHRESHOLD[2:0]
0x50UV_HF[4]THRESHOLD[7:0]
0x51OV_HF[4]THRESHOLD[7:0]
0x52UV_LF[4]THRESHOLD[7:0]
0x53OV_LF[4]THRESHOLD[7:0]
0x54FLT_HF[4]OV_DEB[3:0]UV_DEB[3:0]
0x55FC_LF[4]RSVDTHRESHOLD[2:0]
0x60UV_HF[5]THRESHOLD[7:0]
0x61OV_HF[5]THRESHOLD[7:0]
0x62UV_LF[5]THRESHOLD[7:0]
0x63OV_LF[5]THRESHOLD[7:0]
0x64FLT_HF[5]OV_DEB[3:0]UV_DEB[3:0]
0x65FC_LF[5]RSVDTHRESHOLD[2:0]
0x70UV_HF[6]THRESHOLD[7:0]
0x71OV_HF[6]THRESHOLD[7:0]
0x72UV_LF[6]THRESHOLD[7:0]
0x73OV_LF[6]THRESHOLD[7:0]
0x74FLT_HF[6]OV_DEB[3:0]UV_DEB[3:0]
0x75FC_LF[6]RSVDTHRESHOLD[2:0]
0x9FTI_CONTROLENTER_BISTRSVD
0xA0SEQ_REC_CTLREC_STARTSEQ[1:0]TS_ACKSEQ_ON_ACKSEQ_OFF_ACKSEQ_EXS_ACKSEQ_ENS_ACK
0xA1AMSK_ONRSVDMON[N]
0xA2AMSK_OFFRSVDMON[N]
0xA3AMSK_EXSRSVDMON[N]
0xA4AMSK_ENSRSVDMON[N]
0xA5SEQ_TOUT_MSBMILLISEC[7:0]
0xA6SEQ_TOUT_LSBMILLISEC[7:0]
0xA7SEQ_SYNCPULSE_WIDTH[7:0]
0xA8SEQ_UP_THLDRSVDMON[N]
0xA9SEQ_DN_THLDRSVDMON[N]
0xB0SEQ_ON_EXP[1]ORDER[7:0]
0xB1SEQ_ON_EXP[2]ORDER[7:0]
0xB2SEQ_ON_EXP[3]ORDER[7:0]
0xB3SEQ_ON_EXP[4]ORDER[7:0]
0xB4SEQ_ON_EXP[5]ORDER[7:0]
0xB5SEQ_ON_EXP[6]ORDER[7:0]
0xC0SEQ_OFF_EXP[1]ORDER[7:0]
0xC1SEQ_OFF_EXP[2]ORDER[7:0]
0xC2SEQ_OFF_EXP[3]ORDER[7:0]
0xC3SEQ_OFF_EXP[4]ORDER[7:0]
0xC4SEQ_OFF_EXP[5]ORDER[7:0]
0xC5SEQ_OFF_EXP[6]ORDER[7:0]
0xD0SEQ_EXS_EXP[1]ORDER[7:0]
0xD1SEQ_EXS_EXP[2]ORDER[7:0]
0xD2SEQ_EXS_EXP[3]ORDER[7:0]
0xD3SEQ_EXS_EXP[4]ORDER[7:0]
0xD4SEQ_EXS_EXP[5]ORDER[7:0]
0xD5SEQ_EXS_EXP[6]ORDER[7:0]
0xE0SEQ_ENS_EXP[1]ORDER[7:0]
0xE1SEQ_ENS_EXP[2]ORDER[7:0]
0xE2SEQ_ENS_EXP[3]ORDER[7:0]
0xE3SEQ_ENS_EXP[4]ORDER[7:0]
0xE4SEQ_ENS_EXP[5]ORDER[7:0]
0xE5SEQ_ENS_EXP[6]ORDER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 8-74 shows the codes that are used for access types in this section.

Table 8-74 BANK1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.5.2.1 VMON_CTL Register (Address = 0x10) [Default = X]

VMON_CTL is shown in Table 8-75.

Return to the Summary Table.

Voltage Monitor device control register.

Table 8-75 VMON_CTL Register Field Descriptions
BitFieldTypeDefaultDescription
7:6DIAG_EN_SCALER/W0b Diag EN Scale

00 = No force on GAINSEL of SVS COMPs

01 = Forced to 1x

10 = Forced to 2x

11 = Forced to 4x
5SLP_PWRR/W0b Sleep Power Bit

0 = Sleep low power mode

1 = Sleep high power mode
4RSVDR/WX RSVD
3RESET_PROTR/W0b Reset

0 = Always reads 0

1 = Full device Reset
2SYNC_RSTR/W0b SYNC counter reset (SEQ_ORD_STAT.SYNC_COUNT).


0 = Always reads 0

1 = Reset SYNC counter
1FORCE_SYNCR/W0b Force SYNC assertion

0 =SYNC pin is de-asserted and controlled by the sequence monitoring logic.


1 =SYNC pin is asserted (forced low)
0FORCE_NIRQR/W0b Force NIRQ assertion

0 = NIRQ pin is de-asserted and controlled by interrupt registers faults

1 = NIRQ pin is asserted (forced low)

8.5.2.2 VMON_MISC Register (Address = 0x11) [Default = X]

VMON_MISC is shown in Table 8-76.

Return to the Summary Table.

Miscellaneous voltage monitoring configurations.

Table 8-76 VMON_MISC Register Field Descriptions
BitFieldTypeDefaultDescription
7:4RSVDR/WX RSVD
3EN_TS_OWR/W1b Allow Timestamp recording overwrite

0 = Disabled.
If sequence timestamp data is available in the SEQ_TIME_xSB[N] registers and the SEQ_REC_STAT.TS_RDY bit is set (data not read yet), a new sequence will not overwrite the existing data.


1 = Enabled (default).
Sequence timestamp data is overwritten with a new sequence, irrelevant of the SEQ_REC_STAT.TS_RDY bit.
2EN_SEQ_OWR/W1b Allow Sequence Order recording overwrite

0 = Disabled.
If sequence order data is available in the SEQ_ON_LOG[N], SEQ_OFF_LOG[N], SEQ_EXS_LOG[N], or SEQ_ENS_LOG[N] registers, and the respective SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit is set (data not read yet), a new sequence will not overwrite the existing data.


1 = Enabled (default).
Sequence order data is overwritten with a new sequence, regradless of the SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit.
1REQ_PECR/W0b Require PEC byte (valid only if EN_PEC is 1):

0 = missing PEC byte is treated as good PEC

1 = missing PEC byte is treated as bad PEC, triggering a fault
0EN_PECR/W0b PEC:

0 = PEC disabled (default)

1 = PEC enabled

8.5.2.3 TEST_CFG Register (Address = 0x12) [Default = X]

TEST_CFG is shown in Table 8-77.

Return to the Summary Table.

Built-In Self Test BIST execution configuration.

Table 8-77 TEST_CFG Register Field Descriptions
BitFieldTypeDefaultDescription
7:4RSVDR/WX RSVD
3AT_SHDNR/WX Run BIST when exiting ACTIVE state due to ACT transitioning 1 to 0.
Device ready after tCFG_WB.
This bit cannot be set in OTP/NVM.
Always defaults to 0 when loading configuration from OTP/NVM.
2RESERVEDRX
1:0AT_PORR/WX Run BIST at POR.
Device ready after tCFG_WB.

00b = Valid OTP configuration, skip BIST at POR
01b = Corrupt OTP configuration, run BIST at POR
10b = Corrupt OTP configuration, run BIST at POR
11b = Valid OTP configuration, run BIST at POR

8.5.2.4 IEN_UVHF Register (Address = 0x13) [Default = X]

IEN_UVHF is shown in Table 8-78.

Return to the Summary Table.

High Frequency channel Undervoltage Interrupt Enable register.

Table 8-78 IEN_UVHF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Undervoltage High Frequency fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.5 IEN_UVLF Register (Address = 0x14) [Default = X]

IEN_UVLF is shown in Table 8-79.

Return to the Summary Table.

Low Frequency channel Undervoltage Interrupt Enable register.

Table 8-79 IEN_UVLF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Undervoltage Low Frequency fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.6 IEN_OVHF Register (Address = 0x15) [Default = X]

IEN_OVHF is shown in Table 8-80.

Return to the Summary Table.

High Frequency channel Overvoltage Interrupt Enable register.

Table 8-80 IEN_OVHF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Overvoltage High Frequency fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.7 IEN_OVLF Register (Address = 0x16) [Default = X]

IEN_OVLF is shown in Table 8-81.

Return to the Summary Table.

Low Frequency channel Overvoltage Interrupt Enable register.

Table 8-81 IEN_OVLF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Overvoltage Low Frequency fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.8 IEN_SEQ_ON Register (Address = 0x17) [Default = X]

IEN_SEQ_ON is shown in Table 8-82.

Return to the Summary Table.

Power ON Sequence ACT transition 0 to 1 Interrupt Enable register.

Table 8-82 IEN_SEQ_ON Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Power ON Sequence Fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.9 IEN_SEQ_OFF Register (Address = 0x18) [Default = X]

IEN_SEQ_OFF is shown in Table 8-83.

Return to the Summary Table.

Power OFF Sequence ACT transition 1 to 0 Interrupt Enable register.

Table 8-83 IEN_SEQ_OFF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Power OFF Sequence Fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.10 IEN_SEQ_EXS Register (Address = 0x19) [Default = X]

IEN_SEQ_EXS is shown in Table 8-84.

Return to the Summary Table.

Exit Sleep Sequence SLEEP transition 0 to 1 Interrupt Enable register.

Table 8-84 IEN_SEQ_EXS Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Exit Sleep Sequence Fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.11 IEN_SEQ_ENS Register (Address = 0x1A) [Default = X]

IEN_SEQ_ENS is shown in Table 8-85.

Return to the Summary Table.

Entry Sleep Sequence SLEEP transition 1 to 0 Interrupt Enable register.

Table 8-85 IEN_SEQ_ENS Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Entry Sleep Sequence Fault Interrupt Enable for VIN channel N (1 through 6).


0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.12 IEN_CONTROL Register (Address = 0x1B) [Default = X]

IEN_CONTROL is shown in Table 8-86.

Return to the Summary Table.

Control and Communication Fault Interrupt Enable register.

Table 8-86 IEN_CONTROL Register Field Descriptions
BitFieldTypeDefaultDescription
7:5RSVDR/WX RSVD
4RT_CRC IntR/W0b Runtime register Cyclic Redundancy Check (CRC) fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
3RSVDR/WX RSVD
2TSD IntR/W0b Thermal Shutdown fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
1SYNC IntR/W0b SYNC pin fault (short to supply or ground detected on SYNC pin) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
0PEC IntR/W0b PEC fault (mismatch) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled

8.5.2.13 IEN_TEST Register (Address = 0x1C) [Default = X]

IEN_TEST is shown in Table 8-87.

Return to the Summary Table.

Internal Test and Configuration Load Fault Interrupt Enable register.

Table 8-87 IEN_TEST Register Field Descriptions
BitFieldTypeDefaultDescription
7:4RSVDR/WX RSVD
3ECC_SECR/W0b ECC single-error correction fault (on OTP load) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
2RSVDR/WX RSVD
1BIST_Complete_INTR/W0b Built-In Self-Test complete interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
0BIST_Fail_INTR/W0b Built-In Self-Test fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled Although expected to be always enabled, it is desirable to have the option to disable it.

8.5.2.14 MON_CH_EN Register (Address = 0x1E) [Default = X]

MON_CH_EN is shown in Table 8-88.

Return to the Summary Table.

Channel 1-6 Voltage Monitoring Enable register.

Table 8-88 MON_CH_EN Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Voltage Monitoring Enable for VIN channel N (1 through 6).

0 = Channel Monitor disabled
1 = Channel Monitor enabled

8.5.2.15 VRANGE_MULT Register (Address = 0x1F) [Default = X]

VRANGE_MULT is shown in Table 8-89.

Return to the Summary Table.

Channel 1-6 Voltage Monitoring Range/Scaling register.

Table 8-89 VRANGE_MULT Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W0b Voltage Monitoring Range/Scaling for VIN channel N (1 through 6).


0 = 1x scaling (0.2 V to 1.475 V with 5 mV steps)

1 = 4x scaling (0.8 V to 5.9 V with 20 mV steps)

8.5.2.16 UV_HF[1] Register (Address = 0x20) [Default = 0x00]

UV_HF[1] is shown in Table 8-90.

Return to the Summary Table.

Channel 1 High Frequency channel Undervoltage threshold.

Table 8-90 UV_HF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.17 OV_HF[1] Register (Address = 0x21) [Default = 0xFF]

OV_HF[1] is shown in Table 8-91.

Return to the Summary Table.

Channel 1 High Frequency channel Overvoltage threshold.

Table 8-91 OV_HF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.18 UV_LF[1] Register (Address = 0x22) [Default = 0x00]

UV_LF[1] is shown in Table 8-92.

Return to the Summary Table.

Channel 1 Low Frequency channel Undervoltage threshold.

Table 8-92 UV_LF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.19 OV_LF[1] Register (Address = 0x23) [Default = 0xFF]

OV_LF[1] is shown in Table 8-93.

Return to the Summary Table.

Channel 1 Low Frequency channel Overvoltage threshold.

Table 8-93 OV_LF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.20 FLT_HF[1] Register (Address = 0x24) [Default = 0x00]

FLT_HF[1] is shown in Table 8-94.

Return to the Summary Table.

Channel 1 debounce filter for High Frequency Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-94 FLT_HF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.21 FC_LF[1] Register (Address = 0x25) [Default = X]

FC_LF[1] is shown in Table 8-95.

Return to the Summary Table.

Channel 1 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-95 FC_LF[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b Low frequency cutoff.

000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.22 UV_HF[2] Register (Address = 0x30) [Default = 0x00]

UV_HF[2] is shown in Table 8-96.

Return to the Summary Table.

Channel 2 High Frequency channel Undervoltage threshold.

Table 8-96 UV_HF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.23 OV_HF[2] Register (Address = 0x31) [Default = 0xFF]

OV_HF[2] is shown in Table 8-97.

Return to the Summary Table.

Channel 2 High Frequency channel Overvoltage threshold.

Table 8-97 OV_HF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.24 UV_LF[2] Register (Address = 0x32) [Default = 0x00]

UV_LF[2] is shown in Table 8-98.

Return to the Summary Table.

Channel 2 Low Frequency channel Undervoltage threshold.

Table 8-98 UV_LF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.25 OV_LF[2] Register (Address = 0x33) [Default = 0xFF]

OV_LF[2] is shown in Table 8-99.

Return to the Summary Table.

Channel 2 Low Frequency channel Overvoltage threshold.

Table 8-99 OV_LF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.26 FLT_HF[2] Register (Address = 0x34) [Default = 0x00]

FLT_HF[2] is shown in Table 8-100.

Return to the Summary Table.

Channel 2 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-100 FLT_HF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.27 FC_LF[2] Register (Address = 0x35) [Default = X]

FC_LF[2] is shown in Table 8-101.

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Channel 2 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-101 FC_LF[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.28 UV_HF[3] Register (Address = 0x40) [Default = 0x00]

UV_HF[3] is shown in Table 8-102.

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Channel 3 High Frequency channel Undervoltage threshold.

Table 8-102 UV_HF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.29 OV_HF[3] Register (Address = 0x41) [Default = 0xFF]

OV_HF[3] is shown in Table 8-103.

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Channel 3 High Frequency channel Overvoltage threshold.

Table 8-103 OV_HF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.30 UV_LF[3] Register (Address = 0x42) [Default = 0x00]

UV_LF[3] is shown in Table 8-104.

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Channel 3 Low Frequency channel Undervoltage threshold.

Table 8-104 UV_LF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.31 OV_LF[3] Register (Address = 0x43) [Default = 0xFF]

OV_LF[3] is shown in Table 8-105.

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Channel 3 Low Frequency channel Overvoltage threshold.

Table 8-105 OV_LF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.32 FLT_HF[3] Register (Address = 0x44) [Default = 0x00]

FLT_HF[3] is shown in Table 8-106.

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Channel 3 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-106 FLT_HF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.33 FC_LF[3] Register (Address = 0x45) [Default = X]

FC_LF[3] is shown in Table 8-107.

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Channel 3 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-107 FC_LF[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.34 UV_HF[4] Register (Address = 0x50) [Default = 0x00]

UV_HF[4] is shown in Table 8-108.

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Channel 4 High Frequency channel Undervoltage threshold.

Table 8-108 UV_HF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.35 OV_HF[4] Register (Address = 0x51) [Default = 0xFF]

OV_HF[4] is shown in Table 8-109.

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Channel 4 High Frequency channel Overvoltage threshold.

Table 8-109 OV_HF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.36 UV_LF[4] Register (Address = 0x52) [Default = 0x00]

UV_LF[4] is shown in Table 8-110.

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Channel 4 Low Frequency channel Undervoltage threshold.

Table 8-110 UV_LF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.37 OV_LF[4] Register (Address = 0x53) [Default = 0xFF]

OV_LF[4] is shown in Table 8-111.

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Channel 4 Low Frequency channel Overvoltage threshold.

Table 8-111 OV_LF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.38 FLT_HF[4] Register (Address = 0x54) [Default = 0x00]

FLT_HF[4] is shown in Table 8-112.

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Channel 4 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-112 FLT_HF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.39 FC_LF[4] Register (Address = 0x55) [Default = X]

FC_LF[4] is shown in Table 8-113.

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Channel 4 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-113 FC_LF[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.40 UV_HF[5] Register (Address = 0x60) [Default = 0x00]

UV_HF[5] is shown in Table 8-114.

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Channel 5 High Frequency channel Undervoltage threshold.

Table 8-114 UV_HF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.41 OV_HF[5] Register (Address = 0x61) [Default = 0xFF]

OV_HF[5] is shown in Table 8-115.

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Channel 5 High Frequency channel Overvoltage threshold.

Table 8-115 OV_HF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.42 UV_LF[5] Register (Address = 0x62) [Default = 0x00]

UV_LF[5] is shown in Table 8-116.

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Channel 5 Low Frequency channel Undervoltage threshold.

Table 8-116 UV_LF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.43 OV_LF[5] Register (Address = 0x63) [Default = 0xFF]

OV_LF[5] is shown in Table 8-117.

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Channel 5 Low Frequency channel Overvoltage threshold.

Table 8-117 OV_LF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.44 FLT_HF[5] Register (Address = 0x64) [Default = 0x00]

FLT_HF[5] is shown in Table 8-118.

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Channel 5 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-118 FLT_HF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.45 FC_LF[5] Register (Address = 0x65) [Default = X]

FC_LF[5] is shown in Table 8-119.

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Channel 5 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-119 FC_LF[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.46 UV_HF[6] Register (Address = 0x70) [Default = 0x00]

UV_HF[6] is shown in Table 8-120.

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Channel 6 High Frequency channel Undervoltage threshold.

Table 8-120 UV_HF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.47 OV_HF[6] Register (Address = 0x71) [Default = 0xFF]

OV_HF[6] is shown in Table 8-121.

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Channel 6 High Frequency channel Overvoltage threshold.

Table 8-121 OV_HF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 Vto 5.9 V with 1 LSB = 20 mV.

8.5.2.48 UV_LF[6] Register (Address = 0x72) [Default = 0x00]

UV_LF[6] is shown in Table 8-122.

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Channel 6 Low Frequency channel Undervoltage threshold.

Table 8-122 UV_LF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W0b Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.49 OV_LF[6] Register (Address = 0x73) [Default = 0xFF]

OV_LF[6] is shown in Table 8-123.

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Channel 6 Low Frequency channel Overvoltage threshold.

Table 8-123 OV_LF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2 V to 1.475 V with 1 LSB = 5 mV.
With scaling = 4x, the 8-bit value represents the range 0.8 V to 5.9 V with 1 LSB = 20 mV.

8.5.2.50 FLT_HF[6] Register (Address = 0x74) [Default = 0x00]

FLT_HF[6] is shown in Table 8-124.

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Channel 6 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 8-124 FLT_HF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:4OV_DEB[3:0]R/W0b Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1 µs 1000b = 25.6 µs
0001b = 0.2 µs 1001b = 51.2 µs
0010b = 0.4 µs 1010b = 102.4 µs
0011b = 0.8 µs 1011b = 102.4 µs
0100b = 1.6 µs 1100b = 102.4 µs
0101b = 3.2 µs 1101b = 102.4 µs
0110b = 6.4 µs 1110b = 102.4 µs
0111b = 12.8 µs 1111b = 102.4 µs
3:0UV_DEB[3:0]R/W0b Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1 µs 1000b = 25.6 µs 0001b = 0.2 µs 1001b = 51.2 µs 0010b = 0.4 µs 1010b = 102.4 µs 0011b = 0.8 µs 1011b = 102.4 µs 0100b = 1.6 µs 1100b = 102.4 µs 0101b = 3.2 µs 1101b = 102.4 µs 0110b = 6.4 µs 1110b = 102.4 µs 0111b = 12.8 µs 1111b = 102.4 µs

8.5.2.51 FC_LF[6] Register (Address = 0x75) [Default = X]

FC_LF[6] is shown in Table 8-125.

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Channel 6 Low Frequency Path Cutoff Frequency 3 dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.

Table 8-125 FC_LF[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:3RSVDR/WX RSVD
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250 Hz
011b = 500 Hz
100b = 1 kHz (default)
101b = 2 kHz
110b = 4 kHz
111b = Invalid

8.5.2.52 TI_CONTROL Register (Address = 0x9F) [Default = X]

TI_CONTROL is shown in Table 8-126.

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Manual BIST entry register.

Table 8-126 TI_CONTROL Register Field Descriptions
BitFieldTypeDefaultDescription
7ENTER_BISTR/WX Enter BIST:

0 = Default

1 = Enter BIST
6:0RSVDR/WX RSVD

8.5.2.53 SEQ_REC_CTL Register (Address = 0xA0) [Default = 0x00]

SEQ_REC_CTL is shown in Table 8-127.

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Sequence control register.

Table 8-127 SEQ_REC_CTL Register Field Descriptions
BitFieldTypeDefaultDescription
7REC_STARTR/W0b Software start sequence logging (recording):
0 = Always read 0
1 = Initiate power sequence (selected by SEQ[1:0]) recording.
6:5SEQ[1:0]R/W0b Sequence to record (and compare for faults to corresponding expected sequence order registers):
00b = Power ON (same as ACT 0 to 1)
01b = Power OFF (ACT 1 to 0)
10b = Sleep Exit (SLEEP 0 to 1)
11b = Sleep Entry (SLEEP 1 to 0)
4TS_ACKR/W0b Timestamp data OK to overwrite.
Valid and used only if VMON_MISC.EN_TS_OW=0.

00b = Always read 0
01b = Acknowledge Timestamp data and OK to overwrite.
SEQ_REC_STAT.TS_RDY and SEQ_OW_STAT.TS_OW are cleared.
3SEQ_ON_ACKR/W0b Power ON sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Power ON sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_ON_RDY and SEQ_OW_STAT.SEQ_ON_OW are cleared.
2SEQ_OFF_ACKR/W0b Power OFF sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Power OFF sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_OFF_RDY and SEQ_OW_STAT.SEQ_OFF_OW are cleared.
1SEQ_EXS_ACKR/W0b Sleep Exit sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Sleep Exit sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_EXS_RDY and SEQ_OW_STAT.SEQ_EXS_OW are cleared.
0SEQ_ENS_ACKR/W0b Sleep Entry sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Sleep Entry sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_ENS_RDY and SEQ_OW_STAT.SEQ_ENS_OW are cleared.

8.5.2.54 AMSK_ON Register (Address = 0xA1) [Default = X]

AMSK_ON is shown in Table 8-128.

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Auto-mask ON register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 0 to 1 transitions.

Table 8-128 AMSK_ON Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W111111b Auto-mask on ACT 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

8.5.2.55 AMSK_OFF Register (Address = 0xA2) [Default = X]

AMSK_OFF is shown in Table 8-129.

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Auto-mask OFF register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 1 to 0 transitions.

Table 8-129 AMSK_OFF Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W111111b Auto-mask on ACT 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

8.5.2.56 AMSK_EXS Register (Address = 0xA3) [Default = X]

AMSK_EXS is shown in Table 8-130.

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Auto-mask EXIT register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 0 to 1 transitions.

Table 8-130 AMSK_EXS Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W111111b Auto-mask on SLEEP 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

8.5.2.57 AMSK_ENS Register (Address = 0xA4) [Default = X]

AMSK_ENS is shown in Table 8-131.

Return to the Summary Table.

Auto-mask ENTRY register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 1 to 0 transitions.

Table 8-131 AMSK_ENS Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/WX RSVD
5:0MON[N]R/W111111b Auto-mask on SLEEP 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 6).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

8.5.2.58 SEQ_TOUT_MSB Register (Address = 0xA5) [Default = 0x00]

SEQ_TOUT_MSB is shown in Table 8-132.

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Sequence timeout most significant bits register.

Table 8-132 SEQ_TOUT_MSB Register Field Descriptions
BitFieldTypeDefaultDescription
7:0MILLISEC[7:0]R/W0b ACT and SLEEP transition sequence timeout.
After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active.

0x
0000 = 1 ms
0x
0001 = 2 ms
While the max value is not specified, it is desirable to be able to set this timeout up to 4 s, and at least 256 ms (using only the lower byte at address 0xA6).

8.5.2.59 SEQ_TOUT_LSB Register (Address = 0xA6) [Default = 0x00]

SEQ_TOUT_LSB is shown in Table 8-133.

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Sequence timeout least significant bits register.

Table 8-133 SEQ_TOUT_LSB Register Field Descriptions
BitFieldTypeDefaultDescription
7:0MILLISEC[7:0]R/W0b ACT and SLEEP transition sequence timeout.
After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active.

0x
0000 = 1 ms
0x
0001 = 2 ms
While the max value is not specified, it is desirable to be able to set this timeout up to 4 s, and at least 256 ms (using only the lower byte at address 0xA6).

8.5.2.60 SEQ_SYNC Register (Address = 0xA7) [Default = 0x00]

SEQ_SYNC is shown in Table 8-134.

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Sequence SYNC pulse duration from 50 us to 2600 us.

Table 8-134 SEQ_SYNC Register Field Descriptions
BitFieldTypeDefaultDescription
7:0PULSE_WIDTH[7:0]R/W0b Pulse width for SYNC synchronization pulse.

00000000b = 50µs
00000001b = 60µs
00000010b = 70µs ...

11111101b = 2580µs
11111110b = 2590µs
11111111b = 2600µs

8.5.2.61 SEQ_UP_THLD Register (Address = 0xA8) [Default = 0xDF]

SEQ_UP_THLD is shown in Table 8-135.

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Threshold selection register for up sequence tagging ACT and SLEEP transition 0 to 1 transitions.

Table 8-135 SEQ_UP_THLD Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/W11b RSVD
5:0MON[N]R/W11111b OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power ON and Exit Sleep sequence tagging:
00b = Use OFF threshold (200 mV)
01b = Use UV threshold (UV_LF[N] register)
0b = OFF
1b = UVLF

8.5.2.62 SEQ_DN_THLD Register (Address = 0xA9) [Default = 0x00]

SEQ_DN_THLD is shown in Table 8-136.

Return to the Summary Table.

Threshold selection register for down sequence tagging ACT and SLEEP transition 1 to 0 transitions.

Table 8-136 SEQ_DN_THLD Register Field Descriptions
BitFieldTypeDefaultDescription
7:6RSVDR/W0b RSVD
5:0MON[N]R/W0b OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power OFF and Enter Sleep sequence tagging:
00b = Use OFF threshold (200 mV)
01b = Use UV threshold (UV_LF[N] register)
0b = OFF
1b = UVLF

8.5.2.63 SEQ_ON_EXP[1] Register (Address = 0xB0) [Default = 0x00]

SEQ_ON_EXP[1] is shown in Table 8-137.

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Channel 1 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 1.

Table 8-137 SEQ_ON_EXP[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 1.
This sequence order value is compared with the SEQ_ON_LOG[1] register assigned to the channel during the sequence triggered by ACT.

8.5.2.64 SEQ_ON_EXP[2] Register (Address = 0xB1) [Default = 0x00]

SEQ_ON_EXP[2] is shown in Table 8-138.

Return to the Summary Table.

Channel 2 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 2.

Table 8-138 SEQ_ON_EXP[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 2.
This sequence order value is compared with the SEQ_ON_LOG[2] register assigned to the channel during the sequence triggered by ACT.

8.5.2.65 SEQ_ON_EXP[3] Register (Address = 0xB2) [Default = 0x00]

SEQ_ON_EXP[3] is shown in Table 8-139.

Return to the Summary Table.

Channel 3 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 3

Table 8-139 SEQ_ON_EXP[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 3.
This sequence order value is compared with the SEQ_ON_LOG[3] register assigned to the channel during the sequence triggered by ACT.

8.5.2.66 SEQ_ON_EXP[4] Register (Address = 0xB3) [Default = 0x00]

SEQ_ON_EXP[4] is shown in Table 8-140.

Return to the Summary Table.

Channel 4 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 4.

Table 8-140 SEQ_ON_EXP[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 4.
This sequence order value is compared with the SEQ_ON_LOG[4] register assigned to the channel during the sequence triggered by ACT.

8.5.2.67 SEQ_ON_EXP[5] Register (Address = 0xB4) [Default = 0x00]

SEQ_ON_EXP[5] is shown in Table 8-141.

Return to the Summary Table.

Channel 5 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 5.

Table 8-141 SEQ_ON_EXP[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 5.
This sequence order value is compared with the SEQ_ON_LOG[5] register assigned to the channel during the sequence triggered by ACT.

8.5.2.68 SEQ_ON_EXP[6] Register (Address = 0xB5) [Default = 0x00]

SEQ_ON_EXP[6] is shown in Table 8-142.

Return to the Summary Table.

Channel 6 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 6.

Table 8-142 SEQ_ON_EXP[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power ON sequence order value for channel 6.
This sequence order value is compared with the SEQ_ON_LOG[6] register assigned to the channel during the sequence triggered by ACT.

8.5.2.69 SEQ_OFF_EXP[1] Register (Address = 0xC0) [Default = 0x00]

SEQ_OFF_EXP[1] is shown in Table 8-143.

Return to the Summary Table.

Channel 1 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 1.

Table 8-143 SEQ_OFF_EXP[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 1.
This sequence order value is compared with the SEQ_OFF_LOG[1] register assigned to the channel during the sequence triggered by ACT

8.5.2.70 SEQ_OFF_EXP[2] Register (Address = 0xC1) [Default = 0x00]

SEQ_OFF_EXP[2] is shown in Table 8-144.

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Channel 2 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 2.

Table 8-144 SEQ_OFF_EXP[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 2.
This sequence order value is compared with the SEQ_OFF_LOG[2] register assigned to the channel during the sequence triggered by ACT

8.5.2.71 SEQ_OFF_EXP[3] Register (Address = 0xC2) [Default = 0x00]

SEQ_OFF_EXP[3] is shown in Table 8-145.

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Channel 3 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 3.

Table 8-145 SEQ_OFF_EXP[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 3.
This sequence order value is compared with the SEQ_OFF_LOG[3] register assigned to the channel during the sequence triggered by ACT

8.5.2.72 SEQ_OFF_EXP[4] Register (Address = 0xC3) [Default = 0x00]

SEQ_OFF_EXP[4] is shown in Table 8-146.

Return to the Summary Table.

Channel 4 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 4.

Table 8-146 SEQ_OFF_EXP[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 4.
This sequence order value is compared with the SEQ_OFF_LOG[4] register assigned to the channel during the sequence triggered by ACT

8.5.2.73 SEQ_OFF_EXP[5] Register (Address = 0xC4) [Default = 0x00]

SEQ_OFF_EXP[5] is shown in Table 8-147.

Return to the Summary Table.

Channel 5 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 5.

Table 8-147 SEQ_OFF_EXP[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 5.
This sequence order value is compared with the SEQ_OFF_LOG[5] register assigned to the channel during the sequence triggered by ACT

8.5.2.74 SEQ_OFF_EXP[6] Register (Address = 0xC5) [Default = 0x00]

SEQ_OFF_EXP[6] is shown in Table 8-148.

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Channel 6 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 6.

Table 8-148 SEQ_OFF_EXP[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Power OFF sequence order value for channel 6.
This sequence order value is compared with the SEQ_OFF_LOG[6] register assigned to the channel during the sequence triggered by ACT

8.5.2.75 SEQ_EXS_EXP[1] Register (Address = 0xD0) [Default = 0x00]

SEQ_EXS_EXP[1] is shown in Table 8-149.

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Channel 1 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 1

Table 8-149 SEQ_EXS_EXP[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 1.
This sequence order value is compared with the SEQ_EXS_LOG[1] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.76 SEQ_EXS_EXP[2] Register (Address = 0xD1) [Default = 0x00]

SEQ_EXS_EXP[2] is shown in Table 8-150.

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Channel 2 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 2

Table 8-150 SEQ_EXS_EXP[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 2.
This sequence order value is compared with the SEQ_EXS_LOG[2] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.77 SEQ_EXS_EXP[3] Register (Address = 0xD2) [Default = 0x00]

SEQ_EXS_EXP[3] is shown in Table 8-151.

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Channel 3 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 3

Table 8-151 SEQ_EXS_EXP[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 3.
This sequence order value is compared with the SEQ_EXS_LOG[3] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.78 SEQ_EXS_EXP[4] Register (Address = 0xD3) [Default = 0x00]

SEQ_EXS_EXP[4] is shown in Table 8-152.

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Channel 4 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 4

Table 8-152 SEQ_EXS_EXP[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 4.
This sequence order value is compared with the SEQ_EXS_LOG[4] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.79 SEQ_EXS_EXP[5] Register (Address = 0xD4) [Default = 0x00]

SEQ_EXS_EXP[5] is shown in Table 8-153.

Return to the Summary Table.

Channel 5 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 5

Table 8-153 SEQ_EXS_EXP[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 5.
This sequence order value is compared with the SEQ_EXS_LOG[5] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.80 SEQ_EXS_EXP[6] Register (Address = 0xD5) [Default = 0x00]

SEQ_EXS_EXP[6] is shown in Table 8-154.

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Channel 6 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 6

Table 8-154 SEQ_EXS_EXP[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Exit sequence order value for channel 6.
This sequence order value is compared with the SEQ_EXS_LOG[6] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

8.5.2.81 SEQ_ENS_EXP[1] Register (Address = 0xE0) [Default = 0x00]

SEQ_ENS_EXP[1] is shown in Table 8-155.

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Channel 1 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 1

Table 8-155 SEQ_ENS_EXP[1] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 1.
This sequence order value is compared with the SEQ_ENS_LOG[1] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.82 SEQ_ENS_EXP[2] Register (Address = 0xE1) [Default = 0x00]

SEQ_ENS_EXP[2] is shown in Table 8-156.

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Channel 2 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 2

Table 8-156 SEQ_ENS_EXP[2] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 2.
This sequence order value is compared with the SEQ_ENS_LOG[2] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.83 SEQ_ENS_EXP[3] Register (Address = 0xE2) [Default = 0x00]

SEQ_ENS_EXP[3] is shown in Table 8-157.

Return to the Summary Table.

Channel 3 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 3

Table 8-157 SEQ_ENS_EXP[3] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 3.
This sequence order value is compared with the SEQ_ENS_LOG[3] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.84 SEQ_ENS_EXP[4] Register (Address = 0xE3) [Default = 0x00]

SEQ_ENS_EXP[4] is shown in Table 8-158.

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Channel 4 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 4

Table 8-158 SEQ_ENS_EXP[4] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 4.
This sequence order value is compared with the SEQ_ENS_LOG[4] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.85 SEQ_ENS_EXP[5] Register (Address = 0xE4) [Default = 0x00]

SEQ_ENS_EXP[5] is shown in Table 8-159.

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Channel 5 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 5

Table 8-159 SEQ_ENS_EXP[5] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 5.
This sequence order value is compared with the SEQ_ENS_LOG[5] register assigned to the channel during the sequence triggered by SLEEP.

8.5.2.86 SEQ_ENS_EXP[6] Register (Address = 0xE5) [Default = 0x00]

SEQ_ENS_EXP[6] is shown in Table 8-160.

Return to the Summary Table.

Channel 6 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 6

Table 8-160 SEQ_ENS_EXP[6] Register Field Descriptions
BitFieldTypeDefaultDescription
7:0ORDER[7:0]R/W0b Expected Sleep Entry sequence order value for channel 6.
This sequence order value is compared with the SEQ_ENS_LOG[6] register assigned to the channel during the sequence triggered by SLEEP.