SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.1 Device Nomenclature

Table 12-1 and Table 12-2 show how to decode the function of the device based on its part number.

Table 12-1 Device Thresholds
ORDERING CODEThresholdsVMON1 (V)VMON2 (V)VMON3 (V)VMON4 (V)VMON5 (V)VMON6 (V)

TPS389006ADJRTER

UV_HF/OV_HF

0.47/0.53

0.47/0.53

0.66/0.74

0.66/0.74

0.66/0.74

0.66/0.74

UV_LF/OV_LF

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

0.5/0.7

TPS389006007RTER

UV_HF/OV_HF

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

UV_LF/OV_LF

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

1.4/2.1

Table 12-2 Device Configuration Table
ORDERING CODEFUNCTIONSSCALINGOV/UV DEBOUNCELF CUTOFFI2C ADDRESSBISTSEQ TIMEOUTPEC(1)I2C PULL-UP VOLTAGE (V)

ACT/SLEEP

TPS389006ADJRTER

Monitor LF/HF

1/1/1/1/1/1

102.4μsec1kHzResistor strapat POR25msDisable3.3

Level

TPS389006007RTER

Monitor LF/HF

4/4/4/4/4/4

25.6μsec

1kH

Resistor Strap

At POR

100ms

Disable

3.3

Level

(1) For parts with PEC enabled:
  1. PEC calculation is based on initializing to 0x00.
  2. In case of a PEC violation there needs to be a subsequent I2C transaction before NIRQ is asserted.
  3. If incorrect PEC is given it will assert NIRQ.
  4. If there is an extra byte after successfully writing the correct PEC byte, NIRQ will be asserted and the write will fail.