SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.4 Application Curves

GUID-20230504-SS0I-CVJM-RKJV-Q8GPDSKKM5C8-low.svg Figure 9-2 NIRQ Triggered After an Overvoltage Fault
GUID-20230504-SS0I-GDCH-Z3HD-1XWFH3VTPDQP-low.svg Figure 9-3 NIRQ Triggered After an Undervoltage Fault
GUID-20230504-SS0I-JG4S-MKFF-CD6CBHNGSVN3-low.svg Figure 9-4 NIRQ Not Triggered on Overvoltage Fault with 51.2 us OV Debounce Filter
GUID-20230523-SS0I-MPV4-CVBH-F9Q6RLX5V8NS-low.svg Figure 9-5 NIRQ Triggered on Undervoltage Fault with 12.8 us UV Debounce Filter
GUID-20230504-SS0I-WSFG-0QD7-PDPDNS0ZMKWV-low.svg Figure 9-6 NIRQ Not Triggered on Undervoltage Fault with 25 us UV Debounce Filter
GUID-20230504-SS0I-J5VQ-GSBW-K8D3CDPVHMCR-low.svg Figure 9-7 NIRQ Triggered on Overvoltage Fault with 25 us OV Debounce Filter
GUID-20230504-SS0I-HTCV-DJLH-CCWSTRG83RMM-low.svg Figure 9-8 NIRQ Propogation Delay Resulting from Overvoltage Fault
GUID-20230523-SS0I-VF5L-GWXT-CZKHZZ5RBSLZ-low.svg Figure 9-9 NIRQ Propogation Delay Resulting from Undervoltage Fault
GUID-20230504-SS0I-BSKM-VTFT-2BP0D0KZHG7Z-low.svg Figure 9-10 1 kHz Low Pass Filter Setting. NIRQ Triggered at 1.8 kHz Signal with a 0.8 V DC Component and 200 mVp-p AC Signal. OV and UV Thresholds Set to 0.9V and 0.7V. Reduced the Frequency From 2 kHz Until the NIRQ Pin Went Low.
GUID-20230504-SS0I-ZTNG-HRX6-TF3FG4HD6HGS-low.svg Figure 9-11 250 Hz Low Pass Filter setting. NIRQ Triggered at 455 Hz Signal With a 0.8 V DC Component and 200 mVp-p AC Signal. OV and UV Thresholds Set to 0.9V and 0.7V. Reduced the Frequency From 500 Hz Until the NIRQ Pin Went Low.
GUID-20230504-SS0I-XSMF-36PD-KNVZGKLLKCF2-low.svg Figure 9-12 500 Hz Low Pass Filter Setting. NIRQ Triggered at 0.9 kHz Signal With a 0.8 V DC Component and 200 mVp-p AC Signal. OV and UV Thresholds Set to 0.9V and 0.7V. Reduced the Frequency From 1 kHz Until the NIRQ Pin Went Low.