SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.3.2 ACTIVE Monitoring

The TPS389006 is in ACTIVE state when ACT is High.

VMON monitors high frequency channel levels (copmarator sense path) and low frequency channel levels (ADC sense path) against Under-Voltage High Frequency (UVHF), Over-Voltage High Frequency (OVHF), Under-Voltage Low Frequency (UVLF), and Over-Voltage Low Frequency (OVLF) thresholds.

Some channels can be connected to rails which are controlled by user software. Such channels can be in the OFF state (below the OFF threshold) when the TPS389006 is in an ACTIVE state, and have the UVLF/UVHF interrupts normally disabled. Once these rails are turned ON, the TPS389006 host enables the channels UVLF/UVHF interrupts to allow full monitoring. Similarly, before these rails are turned OFF, the TPS389006 host disables the channels UVLF/UVHF interrupts to avoid false UV violations during the ramp down. As these channels are not part of the sequencing initiated by ACT or SLEEP, their UVLF/UVHF/OVHF interrupts cannot be automatically enabled/disabled using the auto-mask registers. While in the OFF state, only the OVLF thresholds are monitored to ensure the reliability limits are not violated.

Other enabled channels can be in OFF state as a result of the SLEEP 1→0 transition sequence. Those channels are identified by the AMSK_ENS auto-mask register, used to avoid UVLF interrupts (as well as UVHF and OVHF interrupts) during the transition. For those channels in the OFF state and identified by the AMSK_ENS register, only the OVLF thresholds are monitored to ensure the reliability limits are not violated.

Table 8-3 Modes of Operation Summary
ModePin/Bit ConditionIq Monitored- Triggers NIRQ if CHx enabled Status onlyADC/Telemetry
ACTIVEACT=High, Sleep=High1.5mAOVLF, UVLF, OVHF, UVHFOFFEnabled
IDLEACT=Low, Sleep=X230uAOVLFOFFDisabled

SLEEP

ACT=High, SLEEP=Low

Sleep Power bit=1

CHx not assigned to Sleep

1.5mA

OVLF, UVLF, OVHF, UVHFOFF

Enabled

CHx assigned to Sleep (AMSK=1)OVLFOFF
CHx assigned to Sleep (AMSK=0)OVLF, UVLF, OVHF, UVHFOFF

DEEP SLEEP

ACT=High, SLEEP=Low

Sleep Power bit=0

CHx not assigned to Sleep330uAOVHF, UVHF-

Disabled

CHx assigned to Sleep (AMSK=1)No monitoring-
CHx assigned to Sleep (AMSK=0)OVHF, UVHF-