SNVSC50 june   2023 TPS389006

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I2C
      2. 8.3.2 Auto Mask (AMSK)
      3. 8.3.3 PEC
      4. 8.3.4 VDD
      5. 8.3.5 MON
      6. 8.3.6 NIRQ
      7. 8.3.7 ADC
      8. 8.3.8 Time Stamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 Built-In Self Test and Configuration Load
        1. 8.4.1.1 Notes on BIST Execution
      2. 8.4.2 TPS389006 Power ON
      3. 8.4.3 General Monitoring
        1. 8.4.3.1 IDLE Monitoring
        2. 8.4.3.2 ACTIVE Monitoring
        3. 8.4.3.3 Sequence Monitoring 1
          1. 8.4.3.3.1 ACT Transitions 0→1
          2. 8.4.3.3.2 SLEEP Transition 1→0
          3. 8.4.3.3.3 SLEEP Transition 0→1
        4. 8.4.3.4 Sequence Monitoring 2
          1. 8.4.3.4.1 ACT Transition 1→0
    5. 8.5 Register Maps
      1. 8.5.1 BANK0 Registers
      2. 8.5.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

At 2.6 V ≤ VDD ≤ 5.5 V, NIRQ Voltage  = 10 kΩ to VDD, NIRQ load = 10 pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C, typical conditions at VDD = 3.3 V.
MIN NOM MAX UNIT
COMMON PARAMETERS
tBIST POR to ready with BIST, TEST_CFG.AT_POR=1 includes OTP load 12 ms
tNBIST POR to ready without BIST, TEST_CFG.AT_POR=0 includes OTP load 2 ms
BIST BIST time,TEST_CFG.AT_POR=1 or TEST_CFG.AT_SHDN=1 10 ms
tI2C_ACT I2C active from BIST complete 0 µs
tSEQ_Range Sequence timestamp range, ACT or SLEEP edge to max counter 4 s
tSEQ_LSB Sequence timestamp resolution 50 µs
tMON_ACT Monitoring active from ACT rising edge 10 µs
tSEQ_ACT Sequence tagging active from ACT or SLEEP edge 12 µs
tNIRQ Fault detection to NIRQ assertion latency (except OV/UV faults) 25 µs
tPD_NIRQ_1X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 100mV 650 ns
tPD_NIRQ_4X HF fault Propagation detect delay (default deglitch filter) includes digitial delay VIT_OV/UV +/- 400mV 750 ns
tSEQ_ACC Accuracy of sequence timestamp -5 5 %
tGI_R UV & OV debounce range via I2C FLT_HF(N) 0.1 102.4 µs
I2C TIMING CHARACTERISTICS
fSCL Serial clock frequency Standard mode 100 kHz
fSCL Serial clock frequency Fast mode 400 kHz
fSCL Serial clock frequency Fast mode + 1 MHz
tLOW SCL low time Standard mode 4.7 µs
tLOW SCL low time Fast mode 1.3 µs
tLOW SCL low time Fast mode + 0.5 µs
tHIGH SCL high time Standard mode 4 µs
tHIGH SCL high time Fast mode + 0.26 µs
tSU;DAT Data setup time Standard mode 250 ns
tSU;DAT Data setup time Fast mode 100 ns
tSU;DAT Data setup time Fast mode + 50 ns
tHD;DAT Data hold time Standard mode 10 3450 ns
tHD;DAT Data hold time Fast mode 10 900 ns
tHD;DAT Data hold time Fast mode + 10 ns
tSU;STA Setup time for a Start or Repeated Start condition Standard mode 4.7 µs
tSU;STA Setup time for a Start or Repeated Start condition Fast mode 0.6 µs
tSU;STA Setup time for a Start or Repeated Start condition Fast mode + 0.26 µs
tHD:STA Hold time for a Start or Repeated Start condition Standard mode 4 µs
tHD:STA Hold time for a Start or Repeated Start condition Fast mode 0.6 µs
tHD:STA Hold time for a Start or Repeated Start condition Fast mode + 0.26 µs
tBUF Bus free time between a STOP and START condition Standard mode 4.7 µs
tBUF Bus free time between a STOP and START condition Fast mode 1.3 µs
tBUF Bus free time between a STOP and START condition Fast mode + 0.5 µs
tSU;STO Setup time for a Stop condition Standard mode 4 µs
tSU;STO Setup time for a Stop condition Fast mode 0.6 µs
tSU;STO Setup time for a Stop condition Fast mode + 0.26 µs
trDA Rise time of SDA signal Standard mode 1000
trDA Rise time of SDA signal Fast mode 20 300 ns
trDA Rise time of SDA signal Fast mode + 120 ns
tfDA Fall time of SDA signal Standard mode 300 ns
tfDA Fall time of SDA signal Fast mode 1.4 300 ns
tfDA Fall time of SDA signal Fast mode + 6.5 120 ns
trCL Rise time of SCL signal Standard mode 1000 ns
trCL Rise time of SCL signal Fast mode 20 300 ns
trCL Rise time of SCL signal Fast mode + 120 ns
tfCL Fall time of SCL signal Standard mode 300 ns
tfCL Fall time of SCL signal Fast mode 6.5 300 ns
tfCL Fall time of SCL signal Fast mode + 6.5 120 ns
tSP Pulse width of SCL and SDA spikes that are suppressed Standard mode, Fast mode and Fast mode + 50 ns