SLVSG89B April   2021  – January 2024 TPS3899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Hysteresis
      2. 7.3.2 User-Programmable Sense and Reset Time Delay
      3. 7.3.3 RESET/RESET Output
      4. 7.3.4 SENSE Input
        1. 7.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.1 Design Requirements

This design requires voltage supervision on two voltage rails: 3.3V and 1.8V. The voltage rails need to sequence upon power up with the 3.3V coming up at least 25ms followed by the 1.8V rail.

PARAMETER DESIGN REQUIREMENT DESIGN RESULT
Two Rail Voltage Supervision Monitor 3.3V and 1.8V rails Two TPS3899-Q1 devices provide voltage monitoring with 1% accuracy with either an adjustable threshold device or fixed voltage options available in 0.1V variations.
Voltage Rail Sequencing Power up the 3.3V rail first within 25ms followed by 1.8V rail The CTR capacitors on TPS3899DL01-Q1 and TPS3899PL16-Q1 are set to 0.047µF and 0.022µF, respectively, for a reset time delays of 29ms and 13.7ms typical.
Reset Asserting and Timing 1 Reset needs to assert under the reset condition of a push-button press or
VDD < 2.9V after a period of 10ms.		 Reset asserts under the reset condition of a push-button press or
VDD < 2.9V after a period of 13.7ms. The RESEToutput deasserts after 29ms when VDD > 3.05V.
Reset Asserting and Timing 2 Reset needs to assert under the reset condition of VDD < 1.6V after a period of 5ms. Reset asserts under the reset condition of VDD < 1.6V after a period of 6.2ms. The RESET output deasserts after 13.7ms when VDD > 1.68V.
Max device current consumption 1µA Each TPS3899-Q1 requires 125nA typical.