SLVSG89B April   2021  – January 2024 TPS3899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Hysteresis
      2. 7.3.2 User-Programmable Sense and Reset Time Delay
      3. 7.3.3 RESET/RESET Output
      4. 7.3.4 SENSE Input
        1. 7.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-5D4A629C-054A-46EF-A8AF-8B2A5826AA16-low.gif Figure 5-1 DSE Package
6-Pin WSON
TPS3899-Q1 (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 CTR — Capacitor programmable reset delay: The CTR pin offers a user-adjustable delay time when returning from reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to deassert.
2 CTS — Capacitor programmable sense delay: The CTS pin offers a user-adjustable delay time when asserting reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to assert.
3 GND — Ground
4 VDD I Supply voltage pin: Good analog design practice is to place a 0.1µF decoupling capacitor close to this pin.
5 SENSE I This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. When the voltage on the SENSE pin transitions below the negative threshold voltage VIT-, RESET/RESET asserts to active logic after the sense delay set by CTS. When the voltage on the SENSE pin transitions above the positive threshold voltage VIT- + VHYS, RESET/RESET releases to inactive logic (deasserts) after the reset delay set by CTR. For noisy applications, placing a 10nF to
100nF ceramic capacitor close to this pin may be needed for optimum performance.
6 RESET O RESET active-low output that asserts to a logic low state after CTS delay when the monitored voltage on the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic low (asserted) until the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.
6 RESET O RESET active-high output that asserts to a logic high state after CTS delay when the monitored voltage on the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic high (asserted) until the SENSE input rises above VIT- + VHYS and the CTR reset delay expires.