SLVSFM0C September 2020 – January 2024 TPS3899
PRODUCTION DATA
The design requirements, described in Table 7-1, for this design has a defined reset threshold voltage of 2.9V, a sense delay of 60ms, a reset delay of 60ms, and an output current no larger than 500µA.
PARAMETER |
DESIGN REQUIREMENTS |
DESIGN RESULTS |
---|---|---|
Reset Asserting |
Reset needs to assert when under the reset condition of a button press or VDD ≤ 2.9V. |
Reset asserts when under the reset condition of a button press or VDD ≤ 2.93V. |
Reset Asserting Timing |
Reset output needs to assert when the reset conditions are met for 60ms, and needs to de-assert after 60ms of no reset conditions. |
Reset output asserts when the reset conditions are met for 62ms and deasserts after 62ms of no reset conditions. |
Output Current |
The output current must not exceed 500µA. |
The output current is 300µA under the reset condition. |