SNVSCC2F November   2022  – July 2024 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • ASIL-D functional safety-compliant
    • Documentation to aid ISO 26262 system design
    • Systematic capability up to ASIL D
    • Hardware capability up to ASIL D
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C7B
  • Q&A Watchdog to monitor SoC software operation
    • Programmable OPEN/CLOSE watchdog timing through I2C (1ms to 864ms)
    • Start-up delay for SoC boot up initialization (2ms to 3.46s)
    • Programmable maximum violation count (up to 7) before WDO assertion
    • Watchdog disable pin (WDE)
  • Monitor state-of-the art SOCs
    • Three channels with three remote sense (TPS389C03-Q1)
    • Input voltage range: 2.6V to 5.5V
    • Undervoltage lockout (UVLO): 2.6V
    • High threshold accuracy:
    • ± 5mV (–40°C to +125°C)
    • Built-in ADC for voltage readouts
    • Fixed window threshold levels
      • 5mV steps from 0.2V to 1.475V
      • 20mV steps in other ranges
  • Miniature solution and minimal component cost
    • 3mm × 3mm QFN package
    • User adjustable voltage threshold levels via I2C
    • User adjustable glitch immunity and hysteresis levels via I2C
  • Designed for safety applications
    • Error Signal Monitoring (ESM)
      • Programmable ESM delay via I2C (1ms to 864ms)
    • Cyclic Redundancy Checking (CRC)
    • Packet Error Checking (PEC)
    • Active-low open-drain NIRQ, NRST, and WDO outputs