SNVSCC2F November 2022 – July 2024 TPS389C03-Q1
PRODUCTION DATA
The TPS389C03-Q1 has three key functional modes that the device may enter over the course of operation. When no power is applied to the device, it will be in the OFF state where the monitoring channels and the watchdog will be inactive. Once VDD is greater than UVLO, the device will enter the ACTIVE state after the BIST and OTP loading have finished. During the ACTIVE state, the device will be capable of full monitoring and the watchdog will be active. If a BIST failure, double-error detect (DED) during the OTP loading, thermal shutdown, or an address pin fault occurs, the device will enter the FAILSAFE mode. Once in FAILSAFE, NRST and NIRQ are asserted low. To leave the FAILSAFE state, power to the TPS389C03-Q1 must be cycled. Reading register 0x30 in BANK0 provides information on the state of the device. See Section 8.1.1.10 for details. The state diagram drawn in Figure 7-30 follows the progression through each state.