SNVSCC2F November   2022  – July 2024 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 I2C

The TPS389C03-Q1 device follows the I2C protocol (up to 1MHz) to manage communication with host devices such as an MCU or System on Chip (SoC). I2C is a two wire communication protocol implemented using two signals, clock (SCL) and data (SDA). The host device is primary controller of communication. TPS389C03-Q1 device responds over the data line during read or write operation as defined by I2C protocol. Both SCL and SDA signals are open drain topology and can be used in a wired-OR configuration with other devices to share the communication bus. Both SCL and SDA pins need an external pull up resistance to supply voltage (10kΩ recommended).

Figure 7-2 shows the timing relationship between SCL and SDA lines to transfer 1 byte of data. SCL line is always controlled by host. To transfer 1 byte data, host needs to send 9 clocks on SCL. 8 clocks for data and 1 clock for ACK or NACK. SDA line will be controlled by either host or TPS389C03-Q1 device based on the read or write operation. Figure 7-3 and Figure 7-4 highlight the communication protocol flow and which device controls SDA line at various instances during active communication.

TPS389C03-Q1 SCL to SDA timing for 1 byte data transfer Figure 7-2 SCL to SDA timing for 1 byte data transfer
TPS389C03-Q1 I2C write protocol Figure 7-3 I2C write protocol
TPS389C03-Q1 I2C read protocol Figure 7-4 I2C read protocol

Before initiating communication over I2C protocol, host needs to confirm the I2C bus is available for communication. Monitor the SCL and SDA lines, if any line is pulled low, the I2C bus is occupied. Host needs to wait until the bus is available for communication. Once the bus is available for communication, the host can initiate read or write operation by issuing a START condition. Once the I2C communication is complete, release the bus by issuing STOP command. Figure 7-5 shows how to implement START and STOP condition.

TPS389C03-Q1 I2C START and STOP condition Figure 7-5 I2C START and STOP condition

The SDA line may get stuck in logic low level if required number of clocks are not provided by the host. In this scenario, host should provide multiple clocks on SCL line until the SDA line goes high. After this event, host should issue I2C stop command. This will release the I2C bus and other devices can use the I2C bus.

Table 7-1 shows the different functionality available when programming with I2C.

Table 7-1 User Programmable I2C Functions
FUNCTIONSDESCRIPTION
Thresholds for OV/UV- HFAdjustable in 5mV steps from 0.2V to 1.475V and 20mV steps from 0.8V to 5.5V
Thresholds for OV/UV - LFAdjustable in 5mV steps from 0.2V to 1.475V and 20mV steps from 0.8V to 5.5V
Voltage Monitoring scaling1 or 4
Glitch immunity for OV/UV- HF0.1 us to 102.4 us
Low Frequency Cutoff filter 250Hz to 4kHz
Enable sequence timeout1ms to 4s
Packet error checking for I2CEnabling or Disabling
Force NIRQ/NRST/WDO assertionControlled by I2C register
Individual channel MONEnable or Disable
Interrupt disable functionsBIST, PEC, TSD, CRC
ESM Threshold 1ms to 864ms
ESM Debounce 10us to 100us
Reset Delay 200us to 200ms
MAX Violation Count 0 to 7
Watchdog Startup Delay Multiplier 0 to 7
Watchdog Open and Close Window Times 1ms to 864ms
Watchdog Output Delay 200us to 200ms (only applicable for non-latched WDO)
OV/UV/ESM/WDT Mappable individually to NIRQ, NRST, and WDO