SNVSCC2F November 2022 – July 2024 TPS389C03-Q1
PRODUCTION DATA
The register map is designed to support up to 3 channels through register banks, with the following organization:
Bank 0 - Status Register Set Summary
Vendor info and usage registers (bank independent)
Interrupt registers
Status registers
Bank selection register (bank independent)
Protection registers (bank independent)
Device configuration registers (bank independent)
Bank 1 - Configuration Register Set Summary
Vendor info and usage registers (bank independent)
Control registers (device global registers)
Monitor configuration registers (channel specific registers)
Sequence configuration registers (both device global and channel specific registers)
Bank selection register (bank independent)
Protection registers (bank independent)
Device configuration registers (bank independent)
Bank independent registers are accessible at the same address irrespective of the current bank selection. Access to other registers requires the proper bank being selected.
All registers are 8-bit wide, and are loaded at boot with the default value described here or with the OTP value programmed at the factory. Unused registers addresses are reserved for future use and support up to 3 channels.
Write accesses to protected registers (see PROT1/2 details), invalid registers, or valid registers with invalid data, should be NACK'd.
If the default value found in the register map is listed as "X", then the value can be found in TPS389C0300CRTERQ1 OTP Configuration.