SNVSCC2F November   2022  – July 2024 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Packet Error Checking (PEC)

TPS389C03-Q1 supports Packet Error Checking (PEC) as a way to implement Cyclic Redundancy Checking (CRC). PEC is a dynamic CRC that happens only during read or write transactions if enabled. With the initial value of CRC set to 0x00, the PEC uses a CRC-8 represented by the polynomial:

Equation 2. C ( x ) = x 8 + x 2 + x + 1

The polynomial is meant to catch any bit flips or noise in I2C communication which cause data and PEC byte to have a mismatch. The PEC calculation includes all bytes in the transmission, including address, command and data. The PEC calculation does not include ACK or NACK bits or START, STOP or REPEATED START conditions. If PEC is enabled, and the TPS389C03-Q1 is transmitting data, then the TPS389C03-Q1 is responsible for sending the PEC byte. If PEC is enabled, and the TPS389C03-Q1 is reveiving data from the MCU, then the MCU is responsible for sending the PEC byte. In case of faster communications needs like servicing the watchdog the required PEC feature can be effectively used to handle missing PEC information and to avoid triggering faults. Figure 7-8 and Figure 7-9 highlight the communication protocol flow when PEC is required and which device controls SDA line at various instances during active communication.

TPS389C03-Q1 Single Byte Write with PEC Figure 7-8 Single Byte Write with PEC
TPS389C03-Q1 Single Byte Read with PEC Figure 7-9 Single Byte Read with PEC

Table 7-3 summarises the registers associated with a PEC Write command and resulting device behavior. Table 7-4 summarises the registers associated with a PEC Read command and resulting device behavior.

Table 7-3 PEC Write Summary
EN_PEC REQ_PEC PEC_INT Interrupt Status
0 x x PEC byte is not required in write operation, NO NIRQ assertion.
1 0 x A write command missing a PEC byte is treated as OK, the write command will execute and result in a I2C ACT. A write command with an incorrect PEC is treated as an error, the write command will not execute and result in a I2C NACK. NO NIRQ assertion.
1 1 0 A missing PEC is treated as an error, a write command will only execute if the correct PEC byte is provided. I2C communication will still respond with an ACT although write command did not execute. A write command with an incorrect PEC is treated as an error, the write command will not execute and result in a I2C NACK. NO NIRQ assertion.
1 1 1 A missing PEC is treated as an error, a write command will only execute if the correct PEC byte is provided. I2C communication will still respond with an ACT although write command did not execute. A write command with an incorrect PEC is treated as an error, the write command will not execute and result in a I2C NACK. NIRQ is asserted when a write command with a incorrect or missing PEC byte is attempted.
Table 7-4 PEC Read Summary
EN_PEC REQ_PEC PEC_INT Interrupt Status
0 x x I2C read operation will repond with data stored in register, I2C read command will not respond with registers corresponding PEC byte.
1 x x I2C read operation will repond with data stored in register and corresponding PEC byte.