SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2 BANK1 Registers

Table 7-92 lists the memory-mapped registers for the BANK1 registers. All register offset addresses not listed in Table 7-92 should be considered as reserved locations and the register contents should not be modified.

Table 7-92 BANK1 Registers
AddressAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x10VMON_CTLDIAG_EN_SCALESLP_PWRRESERVEDRESET_PROTSYNC_RSTFORCE_SYNCFORCE_NIRQ
0x11VMON_MISCRESERVEDEN_TS_OWEN_SEQ_OWREQ_PECEN_PEC
0x12TEST_CFGRESERVEDAT_SHDNRESERVEDAT_POR
0x13IEN_UVHFMON[N]
0x14IEN_UVLFMON[N]
0x15IEN_OVHFMON[N]
0x16IEN_OVLFMON[N]
0x17IEN_SEQ_ONRESERVEDMON[N]
0x18IEN_SEQ_OFFRESERVEDMON[N]
0x19IEN_SEQ_EXSRESERVEDMON[N]
0x1AIEN_SEQ_ENSRESERVEDMON[N]
0x1BIEN_CONTROLRESERVEDRT_CRC IntRESERVEDTSD IntSYNC IntPEC Int
0x1CIEN_TESTRESERVEDECC_SECRESERVEDBIST_Complete_INTBIST_Fail_INT
0x1DIEN_VENDORRESERVEDRESERVED
0x1EMON_CH_ENMON[N]
0x1FVRANGE_MULTMON[N]
0x20UV_HF[1]THRESHOLD[7:0]
0x21OV_HF[1]THRESHOLD[7:0]
0x22UV_LF[1]THRESHOLD[7:0]
0x23OV_LF[1]THRESHOLD[7:0]
0x24FLT_HF[1]OV_DEB[3:0]UV_DEB[3:0]
0x25FC_LF[1]RESERVEDUV_HF_1 to NRST THRESHOLD[2:0]
0x30UV_HF[2]THRESHOLD[7:0]
0x31OV_HF[2]THRESHOLD[7:0]
0x32UV_LF[2]THRESHOLD[7:0]
0x33OV_LF[2]THRESHOLD[7:0]
0x34FLT_HF[2]OV_DEB[3:0]UV_DEB[3:0]
0x35FC_LF[2]RESERVEDUV_HF_2 to NRST THRESHOLD[2:0]
0x40UV_HF[3]THRESHOLD[7:0]
0x41OV_HF[3]THRESHOLD[7:0]
0x42UV_LF[3]THRESHOLD[7:0]
0x43OV_LF[3]THRESHOLD[7:0]
0x44FLT_HF[3]OV_DEB[3:0]UV_DEB[3:0]
0x45FC_LF[3]RESERVEDUV_HF_3 to NRST THRESHOLD[2:0]
0x50UV_HF[4]THRESHOLD[7:0]
0x51OV_HF[4]THRESHOLD[7:0]
0x52UV_LF[4]THRESHOLD[7:0]
0x53OV_LF[4]THRESHOLD[7:0]
0x54FLT_HF[4]OV_DEB[3:0]UV_DEB[3:0]
0x55FC_LF[4]RESERVEDUV_HF_4 to NRST THRESHOLD[2:0]
0x60UV_HF[5]THRESHOLD[7:0]
0x61OV_HF[5]THRESHOLD[7:0]
0x62UV_LF[5]THRESHOLD[7:0]
0x63OV_LF[5]THRESHOLD[7:0]
0x64FLT_HF[5]OV_DEB[3:0]UV_DEB[3:0]
0x65FC_LF[5]RESERVEDUV_HF_5 to NRST THRESHOLD[2:0]
0x70UV_HF[6]THRESHOLD[7:0]
0x71OV_HF[6]THRESHOLD[7:0]
0x72UV_LF[6]THRESHOLD[7:0]
0x73OV_LF[6]THRESHOLD[7:0]
0x74FLT_HF[6]OV_DEB[3:0]UV_DEB[3:0]
0x75FC_LF[6]RESERVEDUV_HF_6 to NRST THRESHOLD[2:0]
0x80UV_HF[7]THRESHOLD[7:0]
0x81OV_HF[7]THRESHOLD[7:0]
0x82UV_LF[7]THRESHOLD[7:0]
0x83OV_LF[7]THRESHOLD[7:0]
0x84FLT_HF[7]OV_DEB[3:0]UV_DEB[3:0]
0x85FC_LF[7]RESERVEDTHRESHOLD[2:0]
0x90UV_HF[8]THRESHOLD[7:0]
0x91OV_HF[8]THRESHOLD[7:0]
0x92UV_LF[8]THRESHOLD[7:0]
0x93OV_LF[8]THRESHOLD[7:0]
0x94FLT_HF8]OV_DEB[3:0]UV_DEB[3:0]
0x95FC_LF[8]RESERVEDTHRESHOLD[2:0]
0x9FTI_CONTROLENTER_BISTRSVDManual ResetRESERVEDReset delay time
0xA0SEQ_REC_CTLREC_STARTSEQ[1:0]TS_ACKSEQ_ON_ACKSEQ_OFF_ACKSEQ_EXS_ACKSEQ_ENS_ACK
0xA1AMSK_ONMON[N]
0xA2AMSK_OFFMON[N]
0xA3AMSK_EXSMON[N]
0xA4AMSK_ENSMON[N]
0xA5SEQ_TOUT_MSBMILLISEC[7:0]
0xA6SEQ_TOUT_LSBMILLISEC[7:0]
0xA7SEQ_SYNCPULSE_WIDTH[7:0]
0xA8SEQ_UP_THLDMON[N]
0xA9SEQ_DN_THLDMON[N]
0xB0SEQ_ON_EXP[1]ORDER[7:0]
0xB1SEQ_ON_EXP[2]ORDER[7:0]
0xB2SEQ_ON_EXP[3]ORDER[7:0]
0xB3SEQ_ON_EXP[4]ORDER[7:0]
0xB4SEQ_ON_EXP[5]ORDER[7:0]
0xB5SEQ_ON_EXP[6]ORDER[7:0]
0xB6SEQ_ON_EXP[7]ORDER[7:0]
0xB7SEQ_ON_EXP[8]ORDER[7:0]
0xC0SEQ_OFF_EXP[1]ORDER[7:0]
0xC1SEQ_OFF_EXP[2]ORDER[7:0]
0xC2SEQ_OFF_EXP[3]ORDER[7:0]
0xC3SEQ_OFF_EXP[4]ORDER[7:0]
0xC4SEQ_OFF_EXP[5]ORDER[7:0]
0xC5SEQ_OFF_EXP[6]ORDER[7:0]
0xC6SEQ_OFF_EXP[7]ORDER[7:0]
0xC7SEQ_OFF_EXP[8]ORDER[7:0]
0xD0SEQ_EXS_EXP[1]ORDER[7:0]
0xD1SEQ_EXS_EXP[2]ORDER[7:0]
0xD2SEQ_EXS_EXP[3]ORDER[7:0]
0xD3SEQ_EXS_EXP[4]ORDER[7:0]
0xD4SEQ_EXS_EXP[5]ORDER[7:0]
0xD5SEQ_EXS_EXP[6]ORDER[7:0]
0xD6SEQ_EXS_EXP[7]ORDER[7:0]
0xD7SEQ_EXS_EXP[8]ORDER[7:0]
0xE0SEQ_ENS_EXP[1]ORDER[7:0]
0xE1SEQ_ENS_EXP[2]ORDER[7:0]
0xE2SEQ_ENS_EXP[3]ORDER[7:0]
0xE3SEQ_ENS_EXP[4]ORDER[7:0]
0xE4SEQ_ENS_EXP[5]ORDER[7:0]
0xE5SEQ_ENS_EXP[6]ORDER[7:0]
0xE6SEQ_ENS_EXP[7]ORDER[7:0]
0xE7SEQ_ENS_EXP[8]ORDER[7:0]

Complex bit access types are encoded to fit into small table cells. Table 7-93 shows the codes that are used for access types in this section.

Table 7-93 BANK1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.5.2.1 VMON_CTL Register (Address = 0x10) [Reset = 0xX0]

VMON_CTL is shown in Table 7-94.

Return to the Summary Table.

Voltage Monitor device control register.

Table 7-94 VMON_CTL Register Field Descriptions
BitFieldTypeResetDescription
7:6DIAG_EN_SCALER/Wb Diag EN Scale

00 = No force on GAINSEL of SVS COMPs

01 = Forced to
1x

10 = Forced to
2x

11 = Forced to
4x
5SLP_PWRR/Wb Sleep Power Bit

0 = Sleep low power mode

1 = Sleep high power mode
4RESERVEDRb Reserved
3RESET_PROTR/Wb Reset

0 = Always reads
0

1 = Full device Reset
2SYNC_RSTR/Wb SYNC counter reset (SEQ_ORD_STAT.SYNC_COUNT).


0 = Always reads
0

1 = Reset SYNC counter
1FORCE_SYNCR/Wb Force SYNC assertion

0 =SYNC pin is de-asserted and controlled by the sequence monitoring logic.


1 =SYNC pin is asserted (forced low)
0FORCE_NIRQR/Wb Force NIRQ assertion

0 = NIRQ pin is de-asserted and controlled by interrupt registers faults

1 = NIRQ pin is asserted (forced low)

7.5.2.2 VMON_MISC Register (Address = 0x11) [Reset = 0x0C]

VMON_MISC is shown in Table 7-95.

Return to the Summary Table.

Miscellaneous voltage monitoring configurations.

Table 7-95 VMON_MISC Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDRb Reserved
3EN_TS_OWR/W1b Allow Timestamp recording overwrite

0 = Disabled.
If sequence timestamp data is available in the SEQ_TIME_xSB[N] registers and the SEQ_REC_STAT.TS_RDY bit is set (data not read yet), a new sequence does not overwrite the existing data.


1 = Enabled (default).
Sequence timestamp data is overwritten with a new sequence, irrelevant of the SEQ_REC_STAT.TS_RDY bit.
2EN_SEQ_OWR/W1b Allow Sequence Order recording overwrite

0 = Disabled.
If sequence order data is available in the SEQ_ON_LOG[N], SEQ_OFF_LOG[N], SEQ_EXS_LOG[N], or SEQ_ENS_LOG[N] registers, and the respective SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit is set (data not read yet), a new sequence does not overwrite the existing data.


1 = Enabled (default).
Sequence order data is overwritten with a new sequence, regradless of the SEQ_REC_STAT.SEQ_ON_RDY, SEQ_REC_STAT.SEQ_OFF_RDY, SEQ_REC_STAT.SEQ_EXS_RDY, or SEQ_REC_STAT.SEQ_ENS_RDY bit.
1REQ_PECR/Wb Require PEC byte (valid only if EN_PEC is
1):

0 = missing PEC byte is treated as good PEC

1 = missing PEC byte is treated as bad PEC, triggering a fault
0EN_PECR/Wb PEC:

0 = PEC disabled (default)

1 = PEC enabled

7.5.2.3 TEST_CFG Register (Address = 0x12) [Reset = 0xX0]

TEST_CFG is shown in Table 7-96.

Return to the Summary Table.

Built-In Self Test BIST execution configuration.

Table 7-96 TEST_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDRb Reserved
3AT_SHDNR/Wxb Run BIST when exiting ACTIVE state due to ACT transitioning 1 to 0.
Device ready after tCFG_WB.
This bit cannot be set in OTP/NVM.
Always defaults to 0 when loading configuration from OTP/NVM.
2RESERVEDRb
1:0AT_PORR/Wxxb Run BIST at POR.
Device ready after tCFG_WB.

00b = Valid OTP configuration, skip BIST at POR
01b = Corrupt OTP configuration, run BIST at POR
10b = Corrupt OTP configuration, run BIST at POR
11b = Valid OTP configuration, run BIST at POR

7.5.2.4 IEN_UVHF Register (Address = 0x13) [Reset = 0x00]

IEN_UVHF is shown in Table 7-97.

Return to the Summary Table.

High Frequency channel Undervoltage Interrupt Enable register.

Table 7-97 IEN_UVHF Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Undervoltage High Frequency fault Interrupt Enable for VIN channel N (
1 through
8).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.5 IEN_UVLF Register (Address = 0x14) [Reset = 0x00]

IEN_UVLF is shown in Table 7-98.

Return to the Summary Table.

Low Frequency channel Undervoltage Interrupt Enable register.

Table 7-98 IEN_UVLF Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Undervoltage Low Frequency fault Interrupt Enable for VIN channel N (
1 through
8).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.6 IEN_OVHF Register (Address = 0x15) [Reset = 0x00]

IEN_OVHF is shown in Table 7-99.

Return to the Summary Table.

High Frequency channel Overvoltage Interrupt Enable register.

Table 7-99 IEN_OVHF Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Overvoltage High Frequency fault Interrupt Enable for VIN channel N (
1 through
8).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.7 IEN_OVLF Register (Address = 0x16) [Reset = 0x00]

IEN_OVLF is shown in Table 7-100.

Return to the Summary Table.

Low Frequency channel Overvoltage Interrupt Enable register.

Table 7-100 IEN_OVLF Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Overvoltage Low Frequency fault Interrupt Enable for VIN channel N (
1 through
8).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.8 IEN_SEQ_ON Register (Address = 0x17) [Reset = 0x00]

IEN_SEQ_ON is shown in Table 7-101.

Return to the Summary Table.

Power ON Sequence ACT transition 0 to 1 Interrupt Enable register.

Table 7-101 IEN_SEQ_ON Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5:0MON[N]R/Wb Power ON Sequence Fault Interrupt Enable for VIN channel N (
1 through
6).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.9 IEN_SEQ_OFF Register (Address = 0x18) [Reset = 0x00]

IEN_SEQ_OFF is shown in Table 7-102.

Return to the Summary Table.

Power OFF Sequence ACT transition 1 to 0 Interrupt Enable register.

Table 7-102 IEN_SEQ_OFF Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5:0MON[N]R/Wb Power OFF Sequence Fault Interrupt Enable for VIN channel N (
1 through
6).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.10 IEN_SEQ_EXS Register (Address = 0x19) [Reset = 0x00]

IEN_SEQ_EXS is shown in Table 7-103.

Return to the Summary Table.

Exit Sleep Sequence SLEEP transition 0 to 1 Interrupt Enable register.

Table 7-103 IEN_SEQ_EXS Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5:0MON[N]R/Wb Exit Sleep Sequence Fault Interrupt Enable for VIN channel N (
1 through
6).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.11 IEN_SEQ_ENS Register (Address = 0x1A) [Reset = 0x00]

IEN_SEQ_ENS is shown in Table 7-104.

Return to the Summary Table.

Entry Sleep Sequence SLEEP transition 1 to 0 Interrupt Enable register.

Table 7-104 IEN_SEQ_ENS Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5:0MON[N]R/Wb Entry Sleep Sequence Fault Interrupt Enable for VIN channel N (
1 through
6).


0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.12 IEN_CONTROL Register (Address = 0x1B) [Reset = 0x0X]

IEN_CONTROL is shown in Table 7-105.

Return to the Summary Table.

Control and Communication Fault Interrupt Enable register.

Table 7-105 IEN_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4RT_CRC IntR/Wb Runtime register Cyclic Redundancy Check (CRC) fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
3RESERVEDRb Reserved
2TSD IntR/Wb Thermal Shutdown fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
1SYNC IntR/Wb SYNC pin fault (short to supply or ground detected on SYNC pin) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
0PEC IntR/Wb PEC fault (mismatch) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled

7.5.2.13 IEN_TEST Register (Address = 0x1C) [Reset = 0x0X]

IEN_TEST is shown in Table 7-106.

Return to the Summary Table.

Internal Test and Configuration Load Fault Interrupt Enable register.

Table 7-106 IEN_TEST Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDRb Reserved
3ECC_SECR/Wb ECC single-error correction fault (on OTP load) interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
2RESERVEDRb Reserved
1BIST_Complete_INTR/Wb Built-In Self-Test complete interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled
0BIST_Fail_INTR/Wb Built-In Self-Test fault interrupt enable:

0 = Interrupt disabled

1 = Interrupt enabled Although expected to be always enabled, it is desirable to have the option to disable the interrupt.

7.5.2.14 IEN_VENDOR Register (Address = 0x1D) [Reset = 0xX0]

IEN_VENDOR is shown in Table 7-107.

Return to the Summary Table.

Vendor Specific Internal Interrupt Enable register.

Table 7-107 IEN_VENDOR Register Field Descriptions
BitFieldTypeResetDescription
7:0RESERVEDRb Reserved

7.5.2.15 MON_CH_EN Register (Address = 0x1E) [Reset = 0x00]

MON_CH_EN is shown in Table 7-108.

Return to the Summary Table.

Channel 1-8 Voltage Monitoring Enable register.

Table 7-108 MON_CH_EN Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Voltage Monitoring Enable for VIN channel N (
1 through
8).
0 = Channel Monitor disabled
1 = Channel Monitor enabled

7.5.2.16 VRANGE_MULT Register (Address = 0x1F) [Reset = 0x00]

VRANGE_MULT is shown in Table 7-109.

Return to the Summary Table.

Channel 1-8 Voltage Monitoring Range/Scaling register.

Table 7-109 VRANGE_MULT Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb Voltage Monitoring Range/Scaling for VIN channel N (
1 through
8).


0 =
1x scaling (
0.
2V to
1.
475V with
5mV steps)

1 =
4x scaling (
0.
8V to
5.
9V with
20mV steps)

7.5.2.17 UV_HF[1] Register (Address = 0x20) [Reset = 0x00]

UV_HF[1] is shown in Table 7-110.

Return to the Summary Table.

Channel 1 High Frequency channel Undervoltage threshold.

Table 7-110 UV_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.18 OV_HF[1] Register (Address = 0x21) [Reset = 0xFF]

OV_HF[1] is shown in Table 7-111.

Return to the Summary Table.

Channel 1 High Frequency channel Overvoltage threshold.

Table 7-111 OV_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.19 UV_LF[1] Register (Address = 0x22) [Reset = 0x00]

UV_LF[1] is shown in Table 7-112.

Return to the Summary Table.

Channel 1 Low Frequency channel Undervoltage threshold.

Table 7-112 UV_LF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV.
With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.20 OV_LF[1] Register (Address = 0x23) [Reset = 0xFF]

OV_LF[1] is shown in Table 7-113.

Return to the Summary Table.

Channel 1 Low Frequency channel Overvoltage threshold.

Table 7-113 OV_LF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.21 FLT_HF[1] Register (Address = 0x24) [Reset = 0x00]

FLT_HF[1] is shown in Table 7-114.

Return to the Summary Table.

Channel 1 debounce filter for High Frequency Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-114 FLT_HF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.22 FC_LF[1] Register (Address = 0x25) [Reset = 0x14]

FC_LF[1] is shown in Table 7-115.

Return to the Summary Table.

Channel 1 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies. The register also sets the mapping for OV_HF[1]/UV_HF[1] faults to the Reset pin

Table 7-115 FC_LF[1] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_1 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
1 mapped

10 = OV_HF_
1 mapped

11 = UV_HF_
1 and OV_HF_
1 mapped
2:0THRESHOLD[2:0]R/W100b Low frequency cutoff.

000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.23 UV_HF[2] Register (Address = 0x30) [Reset = 0x00]

UV_HF[2] is shown in Table 7-116.

Return to the Summary Table.

Channel 2 High Frequency channel Undervoltage threshold.

Table 7-116 UV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.24 OV_HF[2] Register (Address = 0x31) [Reset = 0xFF]

OV_HF[2] is shown in Table 7-117.

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Channel 2 High Frequency channel Overvoltage threshold.

Table 7-117 OV_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.25 UV_LF[2] Register (Address = 0x32) [Reset = 0x00]

UV_LF[2] is shown in Table 7-118.

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Channel 2 Low Frequency channel Undervoltage threshold.

Table 7-118 UV_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.26 OV_LF[2] Register (Address = 0x33) [Reset = 0xFF]

OV_LF[2] is shown in Table 7-119.

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Channel 2 Low Frequency channel Overvoltage threshold.

Table 7-119 OV_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.27 FLT_HF[2] Register (Address = 0x34) [Reset = 0x00]

FLT_HF[2] is shown in Table 7-120.

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Channel 2 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-120 FLT_HF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.28 FC_LF[2] Register (Address = 0x35) [Reset = 0x14]

FC_LF[2] is shown in Table 7-121.

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Channel 2 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies. The register also sets the mapping for OV_HF[2]/UV_HF[2] faults to the Reset pin

Table 7-121 FC_LF[2] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_2 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
2 mapped

10 = OV_HF_
2 mapped

11 = UV_HF_
2 and OV_HF_
2 mapped
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.29 UV_HF[3] Register (Address = 0x40) [Reset = 0x00]

UV_HF[3] is shown in Table 7-122.

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Channel 3 High Frequency channel Undervoltage threshold.

Table 7-122 UV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.30 OV_HF[3] Register (Address = 0x41) [Reset = 0xFF]

OV_HF[3] is shown in Table 7-123.

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Channel 3 High Frequency channel Overvoltage threshold.

Table 7-123 OV_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.31 UV_LF[3] Register (Address = 0x42) [Reset = 0x00]

UV_LF[3] is shown in Table 7-124.

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Channel 3 Low Frequency channel Undervoltage threshold.

Table 7-124 UV_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.32 OV_LF[3] Register (Address = 0x43) [Reset = 0xFF]

OV_LF[3] is shown in Table 7-125.

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Channel 3 Low Frequency channel Overvoltage threshold.

Table 7-125 OV_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.33 FLT_HF[3] Register (Address = 0x44) [Reset = 0x00]

FLT_HF[3] is shown in Table 7-126.

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Channel 3 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-126 FLT_HF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.34 FC_LF[3] Register (Address = 0x45) [Reset = 0x14]

FC_LF[3] is shown in Table 7-127.

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Channel 3 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.The register also sets the mapping for OV_HF[3]/UV_HF[3] faults to the Reset pin

Table 7-127 FC_LF[3] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_3 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
3 mapped

10 = OV_HF_
3 mapped

11 = UV_HF_
3 and OV_HF_
3 mapped
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.35 UV_HF[4] Register (Address = 0x50) [Reset = 0x00]

UV_HF[4] is shown in Table 7-128.

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Channel 4 High Frequency channel Undervoltage threshold.

Table 7-128 UV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.36 OV_HF[4] Register (Address = 0x51) [Reset = 0xFF]

OV_HF[4] is shown in Table 7-129.

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Channel 4 High Frequency channel Overvoltage threshold.

Table 7-129 OV_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.37 UV_LF[4] Register (Address = 0x52) [Reset = 0x00]

UV_LF[4] is shown in Table 7-130.

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Channel 4 Low Frequency channel Undervoltage threshold.

Table 7-130 UV_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.38 OV_LF[4] Register (Address = 0x53) [Reset = 0xFF]

OV_LF[4] is shown in Table 7-131.

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Channel 4 Low Frequency channel Overvoltage threshold.

Table 7-131 OV_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.39 FLT_HF[4] Register (Address = 0x54) [Reset = 0x00]

FLT_HF[4] is shown in Table 7-132.

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Channel 4 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-132 FLT_HF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.40 FC_LF[4] Register (Address = 0x55) [Reset = 0x14]

FC_LF[4] is shown in Table 7-133.

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Channel 4 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.The register also sets the mapping for OV_HF[4]/UV_HF[4] faults to the Reset pin

Table 7-133 FC_LF[4] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_4 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
4 mapped

10 = OV_HF_
4 mapped

11 = UV_HF_
4 and OV_HF_
4 mapped
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.41 UV_HF[5] Register (Address = 0x60) [Reset = 0x00]

UV_HF[5] is shown in Table 7-134.

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Channel 5 High Frequency channel Undervoltage threshold.

Table 7-134 UV_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.42 OV_HF[5] Register (Address = 0x61) [Reset = 0xFF]

OV_HF[5] is shown in Table 7-135.

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Channel 5 High Frequency channel Overvoltage threshold.

Table 7-135 OV_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.43 UV_LF[5] Register (Address = 0x62) [Reset = 0x00]

UV_LF[5] is shown in Table 7-136.

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Channel 5 Low Frequency channel Undervoltage threshold.

Table 7-136 UV_LF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.44 OV_LF[5] Register (Address = 0x63) [Reset = 0xFF]

OV_LF[5] is shown in Table 7-137.

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Channel 5 Low Frequency channel Overvoltage threshold.

Table 7-137 OV_LF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.45 FLT_HF[5] Register (Address = 0x64) [Reset = 0x00]

FLT_HF[5] is shown in Table 7-138.

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Channel 5 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-138 FLT_HF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.46 FC_LF[5] Register (Address = 0x65) [Reset = 0x14]

FC_LF[5] is shown in Table 7-139.

Return to the Summary Table.

Channel 5 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies.The register also sets the mapping for OV_HF[5]/UV_HF[5] faults to the Reset pin for parts with reset pin

Table 7-139 FC_LF[5] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_5 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
5 mapped

10 = OV_HF_
5 mapped

11 = UV_HF_
5 and OV_HF_
5 mapped
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.47 UV_HF[6] Register (Address = 0x70) [Reset = 0x00]

UV_HF[6] is shown in Table 7-140.

Return to the Summary Table.

Channel 6 High Frequency channel Undervoltage threshold.

Table 7-140 UV_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.48 OV_HF[6] Register (Address = 0x71) [Reset = 0xFF]

OV_HF[6] is shown in Table 7-141.

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Channel 6 High Frequency channel Overvoltage threshold.

Table 7-141 OV_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.49 UV_LF[6] Register (Address = 0x72) [Reset = 0x00]

UV_LF[6] is shown in Table 7-142.

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Channel 6 Low Frequency channel Undervoltage threshold.

Table 7-142 UV_LF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.50 OV_LF[6] Register (Address = 0x73) [Reset = 0xFF]

OV_LF[6] is shown in Table 7-143.

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Channel 6 Low Frequency channel Overvoltage threshold.

Table 7-143 OV_LF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.51 FLT_HF[6] Register (Address = 0x74) [Reset = 0x00]

FLT_HF[6] is shown in Table 7-144.

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Channel 6 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-144 FLT_HF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.52 FC_LF[6] Register (Address = 0x75) [Reset = 0x14]

FC_LF[6] is shown in Table 7-145.

Return to the Summary Table.

Channel 6 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies. The register also sets the mapping for OV_HF[6]/UV_HF[6] faults to the Reset pin for parts with reset pin

Table 7-145 FC_LF[6] Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4:3UV_HF_6 to NRST R/W10b Mapping to NRST

00 = HF faults not mapped

01 = UV_HF_
6 mapped

10 = OV_HF_
6 mapped

11 = UV_HF_
6 and OV_HF_
6 mapped
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.53 UV_HF[7] Register (Address = 0x80) [Reset = 0x00]

UV_HF[7] is shown in Table 7-146.

Return to the Summary Table.

Channel 7 High Frequency channel Undervoltage threshold.

Table 7-146 UV_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.54 OV_HF[7] Register (Address = 0x81) [Reset = 0xFF]

OV_HF[7] is shown in Table 7-147.

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Channel 7 High Frequency channel Overvoltage threshold.

Table 7-147 OV_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.55 UV_LF[7] Register (Address = 0x82) [Reset = 0x00]

UV_LF[7] is shown in Table 7-148.

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Channel 7 Low Frequency channel Undervoltage threshold.

Table 7-148 UV_LF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.56 OV_LF[7] Register (Address = 0x83) [Reset = 0xFF]

OV_LF[7] is shown in Table 7-149.

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Channel 7 Low Frequency channel Overvoltage threshold.

Table 7-149 OV_LF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.57 FLT_HF[7] Register (Address = 0x84) [Reset = 0x00]

FLT_HF[7] is shown in Table 7-150.

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Channel 7 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-150 FLT_HF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.58 FC_LF[7] Register (Address = 0x85) [Reset = 0x14]

FC_LF[7] is shown in Table 7-151.

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Channel 7 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies. The register also sets the mapping for OV_HF[6]/UV_HF[6] faults to the Reset pin for parts with reset pin

Table 7-151 FC_LF[7] Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDRb Reserved
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.59 UV_HF[8] Register (Address = 0x90) [Reset = 0x00]

UV_HF[8] is shown in Table 7-152.

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Channel 8 High Frequency channel Undervoltage threshold.

Table 7-152 UV_HF[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.60 OV_HF[8] Register (Address = 0x91) [Reset = 0xFF]

OV_HF[8] is shown in Table 7-153.

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Channel 8 High Frequency channel Overvoltage threshold.

Table 7-153 OV_HF[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for High Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.61 UV_LF[8] Register (Address = 0x92) [Reset = 0x00]

UV_LF[8] is shown in Table 7-154.

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Channel 8 Low Frequency channel Undervoltage threshold.

Table 7-154 UV_LF[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/Wb Undervoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.62 OV_LF[8] Register (Address = 0x93) [Reset = 0xFF]

OV_LF[8] is shown in Table 7-155.

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Channel 8 Low Frequency channel Overvoltage threshold.

Table 7-155 OV_LF[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0THRESHOLD[7:0]R/W11111111b Overvoltage threshold for Low Frequency component of monitored channel.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling = 1x, the 8-bit value represents the range 0.2V to 1.475V with 1 LSB = 5mV. With scaling = 4x, the 8-bit value represents the range 0.8V to 5.9V with 1 LSB = 20mV.

7.5.2.63 FLT_HF8] Register (Address = 0x94) [Reset = 0x00]

FLT_HF8] is shown in Table 7-156.

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Channel 8 debounce filter for HF Fault. The smallest value supported is 0.4 us, The largest is 102.4 us.

Table 7-156 FLT_HF8] Register Field Descriptions
BitFieldTypeResetDescription
7:4OV_DEB[3:0]R/Wb Overvoltage comparator output debounce time (dont assert until output is stable for debounce time) for High Frequency monitoring path.

0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs
3:0UV_DEB[3:0]R/Wb Undervoltage comparator output debounce time (don't assert until output is stable for debounce time) for High Frequency monitoring path.
0000b = 0.1µs 1000b = 25.6µs 0001b = 0.2µs 1001b = 51.2µs 0010b = 0.4µs 1010b = 102.4µs 0011b = 0.8µs 1011b = 102.4µs 0100b = 1.6µs 1100b = 102.4µs 0101b = 3.2µs 1101b = 102.4µs 0110b = 6.4µs 1110b = 102.4µs 0111b = 12.8µs 1111b = 102.4µs

7.5.2.64 FC_LF[8] Register (Address = 0x95) [Reset = 0x14]

FC_LF[8] is shown in Table 7-157.

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Channel 8 Low Frequency Path Cutoff Frequency 3dB point. The register changes the filter properties of the programmable LPF such that the total frequency response meets these cutoff frequencies. The register also sets the mapping for OV_HF[6]/UV_HF[6] faults to the Reset pin for parts with reset pin

Table 7-157 FC_LF[8] Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDRb Reserved
2:0THRESHOLD[2:0]R/W100b
000b = Invalid
001b = Invalid
010b = 250Hz
011b = 500Hz
100b = 1kHz (default)
101b = 2kHz
110b = 4kHz
111b = Invalid

7.5.2.65 TI_CONTROL Register (Address = 0x9F) [Reset = 0x02]

TI_CONTROL is shown in Table 7-158.

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Manual BIST entry and Reset delay setting register.

Table 7-158 TI_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7ENTER_BISTR/Wb Manual BIST

1= Enter BIST
6RSVDR/Wb RSVD
5Manual ResetR/Wb Manual Reset:

0 = Reset not asserted

1 = Reset asserted
4:3RESERVEDRb Reserved
2:0Reset delay timeR/W10b Reset delay time
000b = 200µs
001b = 1ms
010b = 10ms (default)
011b = 16ms
100b = 20ms
101b = 70ms
110b = 100ms
111b = 200ms

7.5.2.66 SEQ_REC_CTL Register (Address = 0xA0) [Reset = 0x00]

SEQ_REC_CTL is shown in Table 7-159.

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Sequence control register.

Table 7-159 SEQ_REC_CTL Register Field Descriptions
BitFieldTypeResetDescription
7REC_STARTR/Wb Software start sequence logging (recording):
0 = Always read 0
1 = Initiate power sequence (selected by SEQ[1:0]) recording.
6:5SEQ[1:0]R/Wb Sequence to record (and compare for faults to corresponding expected sequence order registers):
00b = Power ON (same as ACT 0 to 1)
01b = Power OFF (ACT 1 to 0)
10b = Sleep Exit (SLEEP 0 to 1)
11b = Sleep Entry (SLEEP 1 to 0)
4TS_ACKR/Wb Timestamp data OK to overwrite.
Valid and used only if VMON_MISC.EN_TS_OW=0.

00b = Always read 0
01b = Acknowledge Timestamp data and OK to overwrite.
SEQ_REC_STAT.TS_RDY and SEQ_OW_STAT.TS_OW are cleared.
3SEQ_ON_ACKR/Wb Power ON sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Power ON sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_ON_RDY and SEQ_OW_STAT.SEQ_ON_OW are cleared.
2SEQ_OFF_ACKR/Wb Power OFF sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Power OFF sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_OFF_RDY and SEQ_OW_STAT.SEQ_OFF_OW are cleared.
1SEQ_EXS_ACKR/Wb Sleep Exit sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Sleep Exit sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_EXS_RDY and SEQ_OW_STAT.SEQ_EXS_OW are cleared.
0SEQ_ENS_ACKR/Wb Sleep Entry sequence data OK to overwrite.
Valid and used only if VMON_MISC.EN_SEQ_OW=0.

00b = Always read 0
01b = Acknowledge Sleep Entry sequence data and OK to overwrite.
SEQ_REC_STAT.SEQ_ENS_RDY and SEQ_OW_STAT.SEQ_ENS_OW are cleared.

7.5.2.67 AMSK_ON Register (Address = 0xA1) [Reset = 0xFF]

AMSK_ON is shown in Table 7-160.

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Auto-mask ON register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 0 to 1 transitions.

Table 7-160 AMSK_ON Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/W11111111b Auto-mask on ACT 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 8).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

7.5.2.68 AMSK_OFF Register (Address = 0xA2) [Reset = 0xFF]

AMSK_OFF is shown in Table 7-161.

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Auto-mask OFF register. This register is used to mask UVLF, UVHF, and OVHF interrupts on ACT transition 1 to 0 transitions.

Table 7-161 AMSK_OFF Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/W11111111b Auto-mask on ACT 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 8).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

7.5.2.69 AMSK_EXS Register (Address = 0xA3) [Reset = 0xFF]

AMSK_EXS is shown in Table 7-162.

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Auto-mask EXIT register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 0 to 1 transitions.

Table 7-162 AMSK_EXS Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/W11111111b Auto-mask on SLEEP 0 to 1 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 8).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

7.5.2.70 AMSK_ENS Register (Address = 0xA4) [Reset = 0xFF]

AMSK_ENS is shown in Table 7-163.

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Auto-mask ENTRY register. This register is used to mask UVLF, UVHF, and OVHF interrupts on SLEEP transition 1 to 0 transitions.

Table 7-163 AMSK_ENS Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/W11111111b Auto-mask on SLEEP 1 to 0 transition for IEN_UVLF, IEN_UVHF, and IEN_OVHF for VIN channel N (1 through 8).

00b = Channel interrupts not auto-masked
01b = Channel interrupts auto-masked

7.5.2.71 SEQ_TOUT_MSB Register (Address = 0xA5) [Reset = 0x00]

SEQ_TOUT_MSB is shown in Table 7-164.

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Sequence timeout most significant bits register.

Table 7-164 SEQ_TOUT_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0MILLISEC[7:0]R/Wb ACT and SLEEP transition sequence timeout.
After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active.


0x0
000 =
1ms

0x0
001 =
2ms
While the max value is not specified, it is desirable to be able to set this timeout up to
4s, and at least
256ms (using only the lower byte at address
0xA
6).

7.5.2.72 SEQ_TOUT_LSB Register (Address = 0xA6) [Reset = 0x00]

SEQ_TOUT_LSB is shown in Table 7-165.

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Sequence timeout least significant bits register.

Table 7-165 SEQ_TOUT_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0MILLISEC[7:0]R/Wb ACT and SLEEP transition sequence timeout.
After the timeout, the auto-masks (AMSK_xxx) are released and the IEN_xVxF interrupts become active.


0x0
000 =
1ms

0x0
001 =
2ms
While the max value is not specified, it is desirable to be able to set this timeout up to
4s, and at least
256ms (using only the lower byte at address
0xA
6).

7.5.2.73 SEQ_SYNC Register (Address = 0xA7) [Reset = 0x00]

SEQ_SYNC is shown in Table 7-166.

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Sequence SYNC pulse duration from 50 us to 2600 us.

Table 7-166 SEQ_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7:0PULSE_WIDTH[7:0]R/Wb Pulse width for SYNC synchronization pulse.

00000000b = 50µs 00000001b = 60µs 00000010b = 70µs ... 11111101b = 2580µs 11111110b = 2590µs 11111111b = 2600µs

7.5.2.74 SEQ_UP_THLD Register (Address = 0xA8) [Reset = 0x1F]

SEQ_UP_THLD is shown in Table 7-167.

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Threshold selection register for up sequence tagging ACT and SLEEP transition 0 to 1 transitions.

Table 7-167 SEQ_UP_THLD Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/W11111b OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power ON and Exit Sleep sequence tagging:
00b = Use OFF threshold (200 mV)
01b = Use UV threshold (UV_LF[N] register)
0b = OFF
1b = UVLF

7.5.2.75 SEQ_DN_THLD Register (Address = 0xA9) [Reset = 0x00]

SEQ_DN_THLD is shown in Table 7-168.

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Threshold selection register for down sequence tagging ACT and SLEEP transition 1 to 0 transitions.

Table 7-168 SEQ_DN_THLD Register Field Descriptions
BitFieldTypeResetDescription
7:0MON[N]R/Wb OFF (200 mV) or UV (UV_LF[N] register) threshold selection for Power OFF and Enter Sleep sequence tagging:
00b = Use OFF threshold (200 mV)
01b = Use UV threshold (UV_LF[N] register)
0b = OFF
1b = UVLF

7.5.2.76 SEQ_ON_EXP[1] Register (Address = 0xB0) [Reset = 0x00]

SEQ_ON_EXP[1] is shown in Table 7-169.

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Channel 1 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 1.

Table 7-169 SEQ_ON_EXP[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 1.
This sequence order value is compared with the SEQ_ON_LOG[1] register assigned to the channel during the sequence triggered by ACT.

7.5.2.77 SEQ_ON_EXP[2] Register (Address = 0xB1) [Reset = 0x00]

SEQ_ON_EXP[2] is shown in Table 7-170.

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Channel 2 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 2.

Table 7-170 SEQ_ON_EXP[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 2.
This sequence order value is compared with the SEQ_ON_LOG[2] register assigned to the channel during the sequence triggered by ACT.

7.5.2.78 SEQ_ON_EXP[3] Register (Address = 0xB2) [Reset = 0x00]

SEQ_ON_EXP[3] is shown in Table 7-171.

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Channel 3 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 3

Table 7-171 SEQ_ON_EXP[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 3.
This sequence order value is compared with the SEQ_ON_LOG[3] register assigned to the channel during the sequence triggered by ACT.

7.5.2.79 SEQ_ON_EXP[4] Register (Address = 0xB3) [Reset = 0x00]

SEQ_ON_EXP[4] is shown in Table 7-172.

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Channel 4 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 4.

Table 7-172 SEQ_ON_EXP[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 4.
This sequence order value is compared with the SEQ_ON_LOG[4] register assigned to the channel during the sequence triggered by ACT.

7.5.2.80 SEQ_ON_EXP[5] Register (Address = 0xB4) [Reset = 0x00]

SEQ_ON_EXP[5] is shown in Table 7-173.

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Channel 5 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 5.

Table 7-173 SEQ_ON_EXP[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 5.
This sequence order value is compared with the SEQ_ON_LOG[5] register assigned to the channel during the sequence triggered by ACT.

7.5.2.81 SEQ_ON_EXP[6] Register (Address = 0xB5) [Reset = 0x00]

SEQ_ON_EXP[6] is shown in Table 7-174.

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Channel 6 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 6.

Table 7-174 SEQ_ON_EXP[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 6.
This sequence order value is compared with the SEQ_ON_LOG[6] register assigned to the channel during the sequence triggered by ACT.

7.5.2.82 SEQ_ON_EXP[7] Register (Address = 0xB6) [Reset = 0x00]

SEQ_ON_EXP[7] is shown in Table 7-175.

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Channel 7 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 7.

Table 7-175 SEQ_ON_EXP[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 7.
This sequence order value is compared with the SEQ_ON_LOG[5] register assigned to the channel during the sequence triggered by ACT.

7.5.2.83 SEQ_ON_EXP[8] Register (Address = 0xB7) [Reset = 0x00]

SEQ_ON_EXP[8] is shown in Table 7-176.

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Channel 8 Power ON sequence order expected value register. This register is used to set the value of the expected power-on sequence order for channel 8.

Table 7-176 SEQ_ON_EXP[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power ON sequence order value for channel 8.
This sequence order value is compared with the SEQ_ON_LOG[6] register assigned to the channel during the sequence triggered by ACT.

7.5.2.84 SEQ_OFF_EXP[1] Register (Address = 0xC0) [Reset = 0x00]

SEQ_OFF_EXP[1] is shown in Table 7-177.

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Channel 1 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 1.

Table 7-177 SEQ_OFF_EXP[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 1.
This sequence order value is compared with the SEQ_OFF_LOG[1] register assigned to the channel during the sequence triggered by ACT

7.5.2.85 SEQ_OFF_EXP[2] Register (Address = 0xC1) [Reset = 0x00]

SEQ_OFF_EXP[2] is shown in Table 7-178.

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Channel 2 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 2.

Table 7-178 SEQ_OFF_EXP[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 2.
This sequence order value is compared with the SEQ_OFF_LOG[2] register assigned to the channel during the sequence triggered by ACT

7.5.2.86 SEQ_OFF_EXP[3] Register (Address = 0xC2) [Reset = 0x00]

SEQ_OFF_EXP[3] is shown in Table 7-179.

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Channel 3 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 3.

Table 7-179 SEQ_OFF_EXP[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 3.
This sequence order value is compared with the SEQ_OFF_LOG[3] register assigned to the channel during the sequence triggered by ACT

7.5.2.87 SEQ_OFF_EXP[4] Register (Address = 0xC3) [Reset = 0x00]

SEQ_OFF_EXP[4] is shown in Table 7-180.

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Channel 4 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 4.

Table 7-180 SEQ_OFF_EXP[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 4.
This sequence order value is compared with the SEQ_OFF_LOG[4] register assigned to the channel during the sequence triggered by ACT

7.5.2.88 SEQ_OFF_EXP[5] Register (Address = 0xC4) [Reset = 0x00]

SEQ_OFF_EXP[5] is shown in Table 7-181.

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Channel 5 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 5.

Table 7-181 SEQ_OFF_EXP[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 5.
This sequence order value is compared with the SEQ_OFF_LOG[5] register assigned to the channel during the sequence triggered by ACT

7.5.2.89 SEQ_OFF_EXP[6] Register (Address = 0xC5) [Reset = 0x00]

SEQ_OFF_EXP[6] is shown in Table 7-182.

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Channel 6 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 6.

Table 7-182 SEQ_OFF_EXP[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 6.
This sequence order value is compared with the SEQ_OFF_LOG[6] register assigned to the channel during the sequence triggered by ACT

7.5.2.90 SEQ_OFF_EXP[7] Register (Address = 0xC6) [Reset = 0x00]

SEQ_OFF_EXP[7] is shown in Table 7-183.

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Channel 7 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 7.

Table 7-183 SEQ_OFF_EXP[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 7.
This sequence order value is compared with the SEQ_OFF_LOG[5] register assigned to the channel during the sequence triggered by ACT

7.5.2.91 SEQ_OFF_EXP[8] Register (Address = 0xC7) [Reset = 0x00]

SEQ_OFF_EXP[8] is shown in Table 7-184.

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Channel 8 Power OFF sequence order expected value register. This register is used to set the value of the expected power-off sequence order for channel 8.

Table 7-184 SEQ_OFF_EXP[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Power OFF sequence order value for channel 8.
This sequence order value is compared with the SEQ_OFF_LOG[6] register assigned to the channel during the sequence triggered by ACT

7.5.2.92 SEQ_EXS_EXP[1] Register (Address = 0xD0) [Reset = 0x00]

SEQ_EXS_EXP[1] is shown in Table 7-185.

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Channel 1 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 1

Table 7-185 SEQ_EXS_EXP[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 1.
This sequence order value is compared with the SEQ_EXS_LOG[1] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.93 SEQ_EXS_EXP[2] Register (Address = 0xD1) [Reset = 0x00]

SEQ_EXS_EXP[2] is shown in Table 7-186.

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Channel 2 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 2

Table 7-186 SEQ_EXS_EXP[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 2.
This sequence order value is compared with the SEQ_EXS_LOG[2] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.94 SEQ_EXS_EXP[3] Register (Address = 0xD2) [Reset = 0x00]

SEQ_EXS_EXP[3] is shown in Table 7-187.

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Channel 3 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 3

Table 7-187 SEQ_EXS_EXP[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 3.
This sequence order value is compared with the SEQ_EXS_LOG[3] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.95 SEQ_EXS_EXP[4] Register (Address = 0xD3) [Reset = 0x00]

SEQ_EXS_EXP[4] is shown in Table 7-188.

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Channel 4 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 4

Table 7-188 SEQ_EXS_EXP[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 4.
This sequence order value is compared with the SEQ_EXS_LOG[4] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.96 SEQ_EXS_EXP[5] Register (Address = 0xD4) [Reset = 0x00]

SEQ_EXS_EXP[5] is shown in Table 7-189.

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Channel 5 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 5

Table 7-189 SEQ_EXS_EXP[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 5.
This sequence order value is compared with the SEQ_EXS_LOG[5] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.97 SEQ_EXS_EXP[6] Register (Address = 0xD5) [Reset = 0x00]

SEQ_EXS_EXP[6] is shown in Table 7-190.

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Channel 6 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 6

Table 7-190 SEQ_EXS_EXP[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 6.
This sequence order value is compared with the SEQ_EXS_LOG[6] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.98 SEQ_EXS_EXP[7] Register (Address = 0xD6) [Reset = 0x00]

SEQ_EXS_EXP[7] is shown in Table 7-191.

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Channel 7 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 7

Table 7-191 SEQ_EXS_EXP[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 7.
This sequence order value is compared with the SEQ_EXS_LOG[5] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.99 SEQ_EXS_EXP[8] Register (Address = 0xD7) [Reset = 0x00]

SEQ_EXS_EXP[8] is shown in Table 7-192.

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Channel 8 Sleep Exit sequence order expected value register. This register is used to set the value of the expected sleep exit sequence order for channel 8

Table 7-192 SEQ_EXS_EXP[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Exit sequence order value for channel 8.
This sequence order value is compared with the SEQ_EXS_LOG[6] register assigned to the channel during the sequence triggered by ACT/ SLEEP.

7.5.2.100 SEQ_ENS_EXP[1] Register (Address = 0xE0) [Reset = 0x00]

SEQ_ENS_EXP[1] is shown in Table 7-193.

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Channel 1 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 1

Table 7-193 SEQ_ENS_EXP[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 1.
This sequence order value is compared with the SEQ_ENS_LOG[1] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.101 SEQ_ENS_EXP[2] Register (Address = 0xE1) [Reset = 0x00]

SEQ_ENS_EXP[2] is shown in Table 7-194.

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Channel 2 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 2

Table 7-194 SEQ_ENS_EXP[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 2.
This sequence order value is compared with the SEQ_ENS_LOG[2] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.102 SEQ_ENS_EXP[3] Register (Address = 0xE2) [Reset = 0x00]

SEQ_ENS_EXP[3] is shown in Table 7-195.

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Channel 3 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 3

Table 7-195 SEQ_ENS_EXP[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 3.
This sequence order value is compared with the SEQ_ENS_LOG[3] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.103 SEQ_ENS_EXP[4] Register (Address = 0xE3) [Reset = 0x00]

SEQ_ENS_EXP[4] is shown in Table 7-196.

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Channel 4 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 4

Table 7-196 SEQ_ENS_EXP[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 4.
This sequence order value is compared with the SEQ_ENS_LOG[4] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.104 SEQ_ENS_EXP[5] Register (Address = 0xE4) [Reset = 0x00]

SEQ_ENS_EXP[5] is shown in Table 7-197.

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Channel 5 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 5

Table 7-197 SEQ_ENS_EXP[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 5.
This sequence order value is compared with the SEQ_ENS_LOG[5] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.105 SEQ_ENS_EXP[6] Register (Address = 0xE5) [Reset = 0x00]

SEQ_ENS_EXP[6] is shown in Table 7-198.

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Channel 6 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 6

Table 7-198 SEQ_ENS_EXP[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 6.
This sequence order value is compared with the SEQ_ENS_LOG[6] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.106 SEQ_ENS_EXP[7] Register (Address = 0xE6) [Reset = 0x00]

SEQ_ENS_EXP[7] is shown in Table 7-199.

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Channel 7 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 7

Table 7-199 SEQ_ENS_EXP[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 7.
This sequence order value is compared with the SEQ_ENS_LOG[5] register assigned to the channel during the sequence triggered by SLEEP.

7.5.2.107 SEQ_ENS_EXP[8] Register (Address = 0xE7) [Reset = 0x00]

SEQ_ENS_EXP[8] is shown in Table 7-200.

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Channel 8 Sleep Entry sequence order expected value register. This register is used to set the value of the expected sleep entry sequence order for channel 8

Table 7-200 SEQ_ENS_EXP[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]R/Wb Expected Sleep Entry sequence order value for channel 8.
This sequence order value is compared with the SEQ_ENS_LOG[6] register assigned to the channel during the sequence triggered by SLEEP.