Built-In Self Test (BIST) is performed:

1. At Power On Reset (POR), if TEST_CFG.AT_POR=1
2. When exiting ACTIVE state due to ACT transitioning from 1→0, if TEST_CFG.AT_SHDN=1

Configuration load from OTP is assisted by ECC (supporting SEC-DED). This is to protect against data integrity issues and to maximize system availability.

During BIST, NIRQ is de-asserted (asserted in case of failure),NRST is asserted (for devices with NRST pin), input pins are ignored, SYNC is tri-stated, and the I²C block is inactive with SDA and SCL de-asserted. The BIST includes device testing to meet the Functional Safety goals outlined in functional safety documentation. Once BIST is completed without failure, I²C is immediately active and the device enters the IDLE sate after loading the configuration data from OTP. If BIST fails and/or ECC reports Double-Error Detection (DED; meant for detecting multiple bit flips when loading data from memory), NIRQ and NRST (for devices with NRST pin) is asserted, the device enters FAILSAFE state, and a best effort attempt is made to keep the I²C function active. TEST_INFO register can provide additional information on the test results.

The detailed behavior upon success/failure of the BIST is controlled by INT_TEST and IEN_TEST registers. Reporting of the BIST results is carried out through:

• NIRQ pin: pulled low depending on the test result and BIST_C and BIST bits in IEN_TEST
• NRST pin (if applicable): pulled low depending on the test result and BIST_C and BIST bits in IEN_TEST
• I_BIST_C and BIST bits in INT_TEST register depending on IEN_TEST settings
• VMON_STAT.ST_BIST_C register bit
• TEST_INFO[3:0] register bits