SLUS660I September 2005 – January 2015 TPS40140
PRODUCTION DATA.
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 3000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Input voltage | VDD, UVLO ≤ VDD | –0.3 | 15 | V | ||
SW1, SW2 | –1 | 40 | ||||
BOOT1, BOOT2, HDRV1, HDRV2 | VSW + 5.5 | |||||
All other pins | –0.3 | 5.5 | ||||
Maximum output current | RT | 25 | µA | |||
Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TPS40140 | UNIT | |
---|---|---|---|
RHH (VQFN) |
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36 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 30.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.4 | |
RθJB | Junction-to-board thermal resistance | 5.9 | |
ψJT | Junction-to-top characterization parameter | 0.2 | |
ψJB | Junction-to-board characterization parameter | 5.9 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.7 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDD INPUT SUPPLY | ||||||
Operating voltage range | 4.5 | 12 | 15 | V | ||
Shutdown current | UVLO_CE1 = UVLO_CE2 = GND | 1 | 10 | µA | ||
BP5 INPUT SUPPLY | ||||||
Operating voltage range | 4.5 | 5.0 | 5.5 | V | ||
BP5 operating current | 2 | 3 | 5 | mA | ||
Rising BP5 turnon | 4.0 | 4.25 | 4.45 | V | ||
BP5 turnoff hysteresis | 100 | 220 | 400 | mV | ||
Standby mode current(1) | UVLO_CEx = 1.7 V | 2.8 | mA | |||
VREG | ||||||
7 V < VDD < 15 V | 4.5 | 5.1 | 5.5 | V | ||
Output current | 0 | 100 | mA | |||
OSCILLATOR, RT | ||||||
Phase frequency accuracy | RRT= 110 kΩ | 300 | kHz | |||
Phase frequency set range | 150 | 1000 | kHz | |||
RT(1) | 25 kΩ ≤ RRT ≤ 500 kΩ | 0.7 | V | |||
UNDERVOLTAGE LOCKOUT (UVLO_CE1, UVLO_CE2) | ||||||
Enable threshold, standby mode | Internal 5VREG regulator enabled | 0.5 | 1.0 | 1.5 | V | |
UVLO threshold | PWM Switching enabled | 1.9 | 2 | 2.1 | V | |
UVLO hysteresis | At the UVLO_CEx pin | 40 | mV | |||
UVLO_CE1, UVLO_CE2 bias current(1) | 1 | μA | ||||
PWM | ||||||
DMAX | Maximum duty cycle per channel(1) | 2-phase, 4-phase, 8-phase, or 16-phase | 87.5% | |||
3-phase, 6-phase, or 12-phase | 83.3% | |||||
tON(min) | Minimum controllable pulse width | 70 | ns | |||
PWM COMPARATOR | ||||||
Input offset voltage | –3 | 3 | mV | |||
VSHARE | ||||||
IVSHR = 0 | 1.785 | 1.8 | 1.815 | V | ||
See(1) | –30 μA < iVSHR < 50 μA | 1.785 | 1.8 | 1.815 | V | |
ERROR AMPLIFIER CH1, ERROR AMPLIFIER CH2 | ||||||
Input common mode range(1) | 0 | 0.7 | 2.0 | V | ||
Input bias current(1) | VFB = 0.7 V | 10 | nA | |||
FBx voltage(1) | 0.6965 | 0.700 | 0.7035 | V | ||
Output source current | VCOMP = 1.1 V, VFB = 0.6 V | 1 | 2 | mA | ||
Output sink current | VCOMP = 1.1 V, VFB = BP5 | 1 | 2 | mA | ||
BW(1) | 8 | 12 | MHz | |||
Open loop gain(1) | 60 | 90 | dB | |||
VOLTAGE TRACKING (TRK1, TRK2) | ||||||
SS source current | After EN, before PWM and during hiccup mode | 5 | 6.0 | 7.3 | µA | |
After first PWM pulse | 10 | 12.5 | 15 | |||
Fault enable threshold(1) | 1.4 | V | ||||
Internal clamp voltage(1) | 2.4 | V | ||||
SS sink resistance(1) | Pulldown resistance | 1 | kΩ | |||
CURRENT SENSE AMPLIFIERS (CS1, CS2) | ||||||
Differential input voltage | –60 | 60 | mV | |||
Input offset voltage | CS1, CS2, trimmed | –2.0 | 0 | 2.0 | mV | |
Ac | Gain transfer to PWM COMP | 5 mV < VCS < 60 mV, VCSRT = 1.5 V | 12 | 13 | 14 | V/V |
Input common mode(1) | 0 | 5.8 | V | |||
CSA | Input bias current | 100 | nA | |||
DIFFERENTIAL AMPLIFIER (DIFFO) | ||||||
Gain | 1.0 V < VOUT < 5.8 V | 0.997 | 1 | 1.003 | V/V | |
Input common mode range(1) | 0 | 5.8 | V | |||
Output source current(1) | VOUT – VVGSNS = 2 V, VDIFFO > 1.98 V, VDD-VOUT > 2 V |
2 | mA | |||
Output source current(1) | VOUT – VVGSNS = 2 V, VDIFFO > 2.02 V VDD – VOUT = 1 V | 1 | ||||
Output sink current(1) | VOUT – VVGSNS = 2 V, VDIFFO > 2.02 V |
2 | ||||
Unity gain bandwidth(1) | 5 | 8 | MHz | |||
Input Impedance, non inverting(1) | VOUT to GND | 60 | kΩ | |||
Input Impedance, inverting(1) | GSNS to DIFFO | 60 | ||||
GATE DRIVERS | ||||||
HDRV1, HDRV2 source on-resistance | VBOOT1, VBOOT2 = 5 V, VSW1 = VSW2 = 0 V, Sourcing 100 mA |
1 | 2 | 3 | Ω | |
HDRV1, HDRV2 sink on-resistance | VVREG = 5 V, VSW1 = VSW2 = 0 V, Sinking 100 mA |
0.5 | 1.2 | 2 | ||
LDRV1, LDRV2 source on-resistance | VVREG = 5 V, VSW1 = VSW2 = 0 V, Sourcing 100 mA |
1 | 2 | 3 | ||
LDRV1, LDRV2 sink on-resistance | VVREG = 5 V, VSW1 = VSW2 = 0 V, Sinking 100 mA |
0.3 | 0.65 | 1 | ||
tRISE | HDRVx rise time(1) | CLOAD= 3.3 nF | 25 | 75 | ns | |
tFALL | HDRVx fall time(1) | CLOAD= 3.3 nF | 25 | 75 | ||
tRISE | LDRVx rise time(1) | CLOAD= 3.3 nF | 25 | 75 | ||
tFALL | LDRVx fall time(1) | CLOAD= 3.3 nF | 20 | 60 | ||
Minimum controllable on-time | CLOAD= 3.3 nF | 50 | ||||
OUTPUT UNDERVOLTAGE FAULT | ||||||
VFB relative to VREF | –19% | –16.5% | –14% | |||
Undervoltage delay(1) | 3 | µs | ||||
CURRENT LIMIT | ||||||
IILIM | Output current | 18.8 | 20 | 21.2 | µA | |
POWER GOOD | ||||||
PGOOD transition low threshold | VFB rising relative to VREF | 10% | 12.5% | 15% | ||
PGOOD transition low threshold | VFB falling relative to VREF | –15% | –12.5% | –10% | ||
PGOOD trip hysteresis | 2% | 5% | ||||
PGOOD delay(1) | 10 | µs | ||||
Low level output voltage, VOL | IPGOOD = 4 mA | 0.35 | 0.4 | V | ||
PGOOD bias current | VPGOOD= 5.0 V | –2 | 1 | 2 | µA | |
RAMP | ||||||
Ramp amplitude(1) | 0.421 | 0.5 | 0.526 | V | ||
VIN BALANCE | ||||||
VIN balance gain, AVB | 0.23 | 0.25 | 0.27 | V/V | ||
THERMAL SHUTDOWN | ||||||
Shutdown temperature(1) | 155 | °C | ||||
Hysteresis(1) | 30 | |||||
DIGITAL CLOCK SIGNAL (CLKIO) | ||||||
Pullup resistance(1) | IOH = 5 mA | 27 | Ω | |||
Pulldown resistance(1) | IOL = 10 mA | 27 | Ω | |||
Output leakage(1) | Tri-state | 1 | µA |