SLUS970C March   2011  – November 2023 TPS40170

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  LDO Linear Regulators and Enable
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Equations for Programming the Input UVLO:
      3. 6.3.3  Oscillator and Voltage Feed-Forward
        1. 6.3.3.1 Calculating the Timing Resistance (RRT)
      4. 6.3.4  Overcurrent Protection and Short-Circuit Protection (OCP and SCP)
      5. 6.3.5  Soft-Start and Fault-Logic
        1. 6.3.5.1 Soft Start During Overcurrent Fault
        2. 6.3.5.2 Equations for Soft Start and Restart Time
      6. 6.3.6  Overtemperature Fault
      7. 6.3.7  Tracking
      8. 6.3.8  Adaptive Drivers
      9. 6.3.9  Start-Up into Pre-Biased Output
      10. 6.3.10 Power Good (PGOOD)
      11. 6.3.11 PGND and AGND
    4. 6.4 Device Functional Modes
      1. 6.4.1 Frequency Synchronization
      2. 6.4.2 Operation Near Minimum VIN (VVIN ≤ 4.5 V)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bootstrap Resistor
      2. 7.1.2 SW Node Snubber Capacitor
      3. 7.1.3 Input Resistor
      4. 7.1.4 LDRV Gate Capacitor
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  List of Materials
        3. 7.2.2.3  Select a Switching Frequency
        4. 7.2.2.4  Inductor Selection (L1)
        5. 7.2.2.5  Output Capacitor Selection (C9)
        6. 7.2.2.6  Peak Current Rating of Inductor
        7. 7.2.2.7  Input Capacitor Selection (C1, C6)
        8. 7.2.2.8  MOSFET Switch Selection (Q1, Q2)
        9. 7.2.2.9  Timing Resistor (R7)
        10. 7.2.2.10 UVLO Programming Resistors (R2, R6)
        11. 7.2.2.11 Boot-Strap Capacitor (C7)
        12. 7.2.2.12 VIN Bypass Capacitor (C18)
        13. 7.2.2.13 VBP Bypass Capacitor (C19)
        14. 7.2.2.14 VDD Bypass Capacitor (C16)
        15. 7.2.2.15 SS Timing Capacitor (C15)
        16. 7.2.2.16 ILIM Resistor (R9, C17)
        17. 7.2.2.17 SCP Multiplier Selection (R5)
        18. 7.2.2.18 Feedback Divider (R10, R11)
        19. 7.2.2.19 Compensation: (R4, R13, C13, C14, C21)
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
      3. 8.1.3 Related Devices
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.11 Boot-Strap Capacitor (C7)

A bootstrap capacitor with a value between 0.1 µF and 0.22 µF must be placed between the BOOT pin and the SW pin. It must be 10 times higher than MOSFET gate capacitance. To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than 250 mV.

Equation 37. GUID-D4C9DC8A-107D-497D-BC18-A8128166EAB7-low.gif